fg_13_01.vhd entity edge_triggered_Dff architecture basic of edge_triggered_Dff architecture hi_fanout of edge_triggered_Dff entity reg4 architecture struct of reg4 configuration fg_13_01 of reg4 -- analyzed, tested ok fg_13_02.vhd package serial_interface_defs -- analyzed, tested ok fg_13_03.vhd entity serial_interface architecture test of serial_interface -- analyzed, tested ok fg_13_04.vhd entity microcontroller architecture structure of microcontroller -- analyzed, tested ok fg_13_05.vhd configuration reg4_gate_level of reg4 entity fg_13_05 architecture test of fg_13_05 configuration fg_13_05_test of fg_13_05 -- analyzed, tested ok fg_13_06.vhd package counter_types entity add_1 architecture boolean_eqn of add_1 entity buf4 architecture basic of buf4 entity counter architecture registered of counter -- analyzed, tested ok fg_13_07.vhd configuration counter_down_to_gate_level of counter entity fg_13_07 architecture test of fg_13_07 -- analyzed, tested ok fg_13_08.vhd configuration full of counter entity fg_13_08 architecture test of fg_13_08 -- analyzed, tested ok fg_13_09.vhd entity alarm_clock architecture top_level of alarm_clock -- analyzed, tested ok fg_13_10.vhd entity reg architecture gate_level of reg -- analyzed, tested ok fg_13_11.vhd entity controller architecture structural of controller -- analyzed, tested ok fg_13_12.vhd configuration controller_with_timing of circuit -- analyzed, tested ok fg_13_13.vhd entity computer_system architecture structure of computer_system -- analyzed, tested ok fg_13_14.vhd entity decoder_3_to_8 architecture basic of decoder_3_to_8 -- analyzed, tested ok fg_13_15.vhd configuration computer_structure of computer_system -- analyzed, tested ok fg_13_17.vhd entity single_board_computer architecture structural of single_board_computer -- analyzed, tested ok fg_13_18.vhd entity XYZ3000_cpu architecture full_function of XYZ3000_cpu entity memory_array architecture behavioral of memory_array configuration intermediate of single_board_computer -- analyzed, tested ok fg_13_19.vhd entity nand3 architecture behavioral of nand3 entity logic_block architecture ideal of logic_block -- analyzed, tested ok fg_13_20.vhd entity control_section architecture structural of control_section -- analyzed, tested ok (workaround mt023) fg_13_21.vhd entity reg architecture gate_level of reg -- analyze before fg_13_20.vhd, analyzed, tested ok fg_13_22.vhd configuration controller_with_timing of control_section -- analyzed, tested ok (workaround mt023) fg_13_23.vhd entity nor_gate architecture primitive of nor_gate entity interlock_control architecture detailed_timing of interlock_control -- analyzed, tested ok fg_13_24.vhd configuration interlock_control_with_estimates of interlock_control configuration interlock_control_with_actual of interlock_control -- analyzed, tested ok fg_13_25.vhd entity nand3 architecture basic of nand3 entity misc_logic architecture gate_level of misc_logic -- analyzed, tested ok fg_13_26.vhd configuration misc_logic_reconfigured of misc_logic -- analyzed, tested ok ch_13_01.vhd entity ch_13_01 architecture test of ch_13_01 entity nand2 configuration ch_13_01_test of ch_13_01 -- analyzed (error expected), ok <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>