-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.12 




-- ENTITY DECLERATION OF TEST BENCH FOR D-FLIPFLOP :

ENTITY flipflop_test IS END flipflop_test;
--



-- TEST BENCH FOR ASSIGNING AND GUARDING ARCHITECTURES OF D-FLIPFLOP :

ARCHITECTURE input_output OF flipflop_test IS
  COMPONENT ff PORT (d, c : IN BIT; q, qb : OUT BIT); END COMPONENT;
  FOR c1 : ff USE ENTITY WORK.d_flipflop (assigning);
  FOR c2 : ff USE ENTITY WORK.d_flipflop (guarding);
  SIGNAL dd, cc, q1, q2, qb1, qb2 : BIT;
BEGIN
  cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc;
  dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd;
  c1: ff PORT MAP (dd, cc, q1, qb1);
  c2: ff PORT MAP (dd, cc, q2, qb2);
END input_output;
--