-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.16 




-- ENTITY DECLERATION OF TEST BENCH FOR D-FLIPFLOP :

ENTITY flipflop_test IS END flipflop_test;
--



-- TEST BENCH FOR GUARDING ARCHITECTURE OF DE-FLIPFLOP :

ARCHITECTURE input_output OF flipflop_test IS
  COMPONENT ff1 PORT (d, e, c : IN BIT; q, qb : OUT BIT); END COMPONENT;
  FOR c1 : ff1 USE ENTITY WORK.de_flipflop (guarding);
  SIGNAL dd, ee, cc, q1, qb1 : BIT;
BEGIN
  cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc;
  dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd;
  ee <= '1', '0' AFTER 2200 NS;
  c1: ff1 PORT MAP (dd, ee, cc, q1, qb1);
END input_output;
--