-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.29 




-- ENTITY DECLERATION OF 8-to-1 MULTIPLEXER :

USE WORK.basic_utilities.ALL;
ENTITY mux_8_to_1 IS
  PORT (i7, i6, i5, i4, i3, i2, i1, i0 : IN qit;
        s7, s6, s5, s4, s3, s2, s1, s0 : IN qit; z : OUT qit );
END mux_8_to_1;
--



-- MULTIPLE_GUARDED ARCHITECTURE OF 8-to-1 MULTIPLEXER :


ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS
  FUNCTION wire (a, b : qit) RETURN qit IS
    CONSTANT qit_and_table : qit_2d := (
                             ('0','X','0','X'),
                             ('X','1','1','X'),
                             ('0','1','Z','X'),
                             ('X','X','X','X'));
  BEGIN
    RETURN qit_and_table (a, b);
  END wire;
  FUNCTION wiring ( drivers : qit_vector) RETURN qit IS
    VARIABLE accumulate : qit := 'Z';
  BEGIN
    FOR i IN drivers'RANGE LOOP
      accumulate := wire(accumulate, drivers(i));
    END LOOP;
    RETURN accumulate;
  END wiring;
  SIGNAL t : wiring qit BUS;
BEGIN
  b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN  t <= GUARDED i7; END BLOCK;
  b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN  t <= GUARDED i6; END BLOCK;
  b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN  t <= GUARDED i5; END BLOCK;
  b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN  t <= GUARDED i4; END BLOCK;
  b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN  t <= GUARDED i3; END BLOCK;
  b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN  t <= GUARDED i2; END BLOCK;
  b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN  t <= GUARDED i1; END BLOCK;
  b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN  t <= GUARDED i0; END BLOCK;
  z <= t;
END multiple_guarded_assignments;
--