-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.39 




-- ENTITY DECLERATION OF 2-INPUT NAND :

USE WORK.basic_utilities.ALL; 
ENTITY nand2 IS 
  PORT (a, b : IN qit; y : OUT qit);
  CONSTANT tplh : TIME := 10 NS;
  CONSTANT tphl : TIME := 12 NS;
END nand2;
--



-- VHDL DESCRIPTION FOR 2-INPUT NAND WITH OPEN COLLECTOR OUTPUT :

ARCHITECTURE open_output OF nand2 IS
BEGIN
  y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE
       'Z' AFTER tplh WHEN (a AND b) = '0' ELSE
       'X' AFTER tphl;
END open_output;
--