-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.41 




-- ENTITY DECLERATION OF TTL 74LS03 :

USE WORK.basic_utilities.ALL;
ENTITY sn7403 IS
  PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit);
END sn7403;
--



-- VHDL DESCRIPTION FOR TTL 74LS03 :

ARCHITECTURE structural OF sn7403 IS
  COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT;
  FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output);
BEGIN
  g1: nand2 PORT MAP ( a1, b1, y1 );
  g2: nand2 PORT MAP ( a2, b2, y2 );
  g3: nand2 PORT MAP ( a3, b3, y3 );
  g4: nand2 PORT MAP ( a4, b4, y4 );
END structural; 
--