-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.37 




-- ENTITY DECLERATION OF DETECTOR :

ENTITY detector IS 
  PORT (x, clk : IN BIT; z : OUT BIT);
END detector;
--



-- VHDL DESCRIPTION FOR 1011 DETECTOR :
(More than 1 state can simultaneously be active.) 

ARCHITECTURE multiple_state_machine OF detector IS
  FUNCTION oring (sources : BIT_VECTOR) RETURN BIT IS
    VARIABLE value : BIT := '0';
  BEGIN
    FOR i IN sources'RANGE LOOP
      value := value OR sources(i);
    END LOOP;
    RETURN value;
  END oring;
  SUBTYPE state IS oring BIT;
  TYPE state_vector IS ARRAY (INTEGER RANGE <>) OF state;
  SIGNAL s : state_vector (1 TO 4) REGISTER := "1000"; 
BEGIN
  clocking : BLOCK (clk = '1' AND NOT clk'STABLE)
  BEGIN
    s1: BLOCK (s(1) = '1' AND GUARD)
    BEGIN
      s(1) <= GUARDED '1' WHEN x = '0' ELSE '0';
      s(2) <= GUARDED '1' WHEN x = '1' ELSE '0';
    END BLOCK s1;
    s2: BLOCK (s(2) = '1' AND GUARD)
    BEGIN
      s(3) <= GUARDED '1' WHEN x = '0' ELSE '0';
      s(2) <= GUARDED '1' WHEN x = '1' ELSE '0';
    END BLOCK s2;
    s3: BLOCK (s(3) = '1' AND GUARD)
    BEGIN
      s(1) <= GUARDED '1' WHEN x = '0' ELSE '0';
      s(4) <= GUARDED '1' WHEN x = '1' ELSE '0';
    END BLOCK s3;
    s4: BLOCK (s(4) = '1' AND GUARD)
    BEGIN
      s(3) <= GUARDED '1' WHEN x = '0' ELSE '0';
      s(2) <= GUARDED '1' WHEN x = '1' ELSE '0';
      z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0';
    END BLOCK s4;
    s <= GUARDED "0000"; 
  END BLOCK clocking;
END multiple_state_machine;

--