-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 7.36 




-- ENTITY DECLERATION OF DETECTOR :

ENTITY detector IS 
  PORT (x, clk : IN BIT; z : OUT BIT);
END detector;
--



-- VHDL DESCRIPTION FOR 1011 DETECTOR :

ARCHITECTURE singular_state_machine OF detector IS
  TYPE state IS (reset, got1, got10, got101);
  TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state;
  FUNCTION one_of (sources : state_vector) RETURN state IS
  BEGIN
    RETURN sources(sources'LEFT);
  END one_of;
  SIGNAL current : one_of state REGISTER := reset;
BEGIN
  clocking : BLOCK (clk = '1' AND NOT clk'STABLE)
  BEGIN
    s1: BLOCK ( current = reset AND GUARD )
    BEGIN
      current <= GUARDED got1 WHEN x = '1' ELSE reset;
    END BLOCK s1;
    s2: BLOCK ( current = got1 AND GUARD )
    BEGIN
      current <= GUARDED got10 WHEN x = '0' ELSE got1;
    END BLOCK s2;
    s3: BLOCK ( current = got10 AND GUARD )
    BEGIN
      current <= GUARDED got101 WHEN x = '1' ELSE reset;
    END BLOCK s3;
    s4: BLOCK ( current = got101 AND GUARD)
    BEGIN
      current <= GUARDED got1 WHEN x = '1' ELSE got10;
      z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0';
    END BLOCK s4;
  END BLOCK clocking;
END singular_state_machine;
--