Description Direction In the simulation optimization project, we are looking at ways of improving RTL level simulation of hardware described in VHDL. The work considers various modelling styles tools and Techniques for achieving a better performance. We have concentrated on : Performance improvement by reducing activities in event driven simulation environment, Developing optimized models for common components such as memories and cache structures, and Developing concurrent simulation models for handling simulation of arrays and vectors. We have been using the Parwan CPU model for bencmarking our developed techniques and strategies. CPU Model Because of its simple design Parvan is used for demonstration of our modelling techniques. This is a simple 8 bit processor with a very small set of instructions. It has 9 control states, 7 RT level components ans a * byte momory. This CPU and its manual design is shown in refrence . A dataflow synthesizable Parwan model, shown on this page will be used as the base of all our comparisons. Activity Reduction Event driven simulation speed can be improved by reducing events that cause unnecessary simulation activities. Events due to data scheduling account for a large portion of simulation time. We have developed RTL component modeling strategies with explicit scheduling and reduced activity. This paper discusses activity suppression techniques and their implementation in VHDL. [See the related paper] Concurrent Simulation Simulation time is a crucial bottleneck in the design process. In many cases a simulation is run several times with different inputs. Making such simulation runs parallel will significantly reduce the simulation time. In this paper we are introducing a concurrent simulation implemented with standard VHDL'93 to optimize simulation time of RTL level models. [See the related paper] Current Status .................. Under Construction ...........

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