/* jefferson -- Sun Apr 9 17:25:58 1995 Initial design_analyzer Variable Values */ .synopsys_dc.setup = ".synopsys_dc.setup" annotation_control = 64 arch = "sparc" arch_init_path = "/opt/digital/synopsys3.2b/sparc/motif/syn/uid" atpg_test_asynchronous_pins = "true" auto_link_disable = "false" auto_link_options = "-all" auto_wire_load_selection = "true" bc_enable_chaining = "true" bc_enable_multi_cycle = "true" bin_path = "/opt/digital/synopsys3.2b/sparc/syn/bin" bit_mapper_name_layer.blue = 65535 bit_mapper_name_layer.green = 65535 bit_mapper_name_layer.red = 65535 bit_mapper_name_layer.visible = "true" bus_cell_layer.blue = 65535 bus_cell_layer.green = 65535 bus_cell_layer.line_max = 4 bus_cell_layer.line_min = 2 bus_cell_layer.line_width = 400 bus_cell_layer.red = 0 bus_cell_layer.scalable_lines = "true" bus_cell_layer.visible = "true" bus_cell_name_layer.blue = 65535 bus_cell_name_layer.green = 65535 bus_cell_name_layer.red = 65535 bus_cell_name_layer.visible = "true" bus_compound_name_layer.blue = 65535 bus_compound_name_layer.green = 65535 bus_compound_name_layer.red = 65535 bus_compound_name_layer.visible = "false" bus_dimension_separator_style = "][" bus_extraction_style = "%s[%d:%d]" bus_inference_descending_sort = "true" bus_inference_style = "" bus_minus_style = "-%d" bus_naming_style = "%s[%d]" bus_net_layer.blue = 65535 bus_net_layer.green = 38666 bus_net_layer.line_width = 3 bus_net_layer.red = 0 bus_net_layer.scalable_lines = "false" bus_net_layer.visible = "true" bus_net_name_layer.blue = 65535 bus_net_name_layer.green = 65535 bus_net_name_layer.red = 65535 bus_net_name_layer.visible = "false" bus_osc_layer.blue = 0 bus_osc_layer.green = 65535 bus_osc_layer.line_max = 4 bus_osc_layer.line_min = 2 bus_osc_layer.line_width = 400 bus_osc_layer.red = 65535 bus_osc_layer.scalable_lines = "true" bus_osc_layer.visible = "true" bus_osc_name_layer.blue = 65535 bus_osc_name_layer.green = 65535 bus_osc_name_layer.red = 65535 bus_osc_name_layer.visible = "true" bus_pin_name_layer.blue = 65535 bus_pin_name_layer.green = 65535 bus_pin_name_layer.red = 65535 bus_pin_name_layer.visible = "false" bus_port_layer.blue = 0 bus_port_layer.green = 65535 bus_port_layer.line_max = 4 bus_port_layer.line_min = 2 bus_port_layer.line_width = 400 bus_port_layer.red = 65535 bus_port_layer.scalable_lines = "true" bus_port_layer.visible = "true" bus_port_name_layer.blue = 65535 bus_port_name_layer.green = 65535 bus_port_name_layer.red = 65535 bus_port_name_layer.visible = "true" bus_range_separator_style = ":" bus_ripper_layer.blue = 0 bus_ripper_layer.green = 65535 bus_ripper_layer.line_max = 3 bus_ripper_layer.line_width = 200 bus_ripper_layer.red = 65535 bus_ripper_layer.scalable_lines = "true" bus_ripper_layer.visible = "true" bus_ripper_name_layer.blue = 65535 bus_ripper_name_layer.green = 65535 bus_ripper_name_layer.red = 65535 bus_ripper_name_layer.visible = "true" cache_dir_chmod_octal = "777" cache_file_chmod_octal = "666" cache_read = {"~"} cache_read_info = "false" cache_write = "~" cache_write_info = "false" cell_layer.blue = 0 cell_layer.green = 65535 cell_layer.line_max = 3 cell_layer.line_width = 200 cell_layer.red = 65535 cell_layer.scalable_lines = "true" cell_layer.visible = "true" cell_name_layer.blue = 65535 cell_name_layer.green = 65535 cell_name_layer.red = 65535 cell_name_layer.visible = "false" cell_ref_name_layer.blue = 65535 cell_ref_name_layer.green = 65535 cell_ref_name_layer.red = 65535 cell_ref_name_layer.visible = "true" change_names_update_inst_tree = "true" channel_width_denominator = 7 channel_width_numerator = 4 clock_layer.blue = 0 clock_layer.green = 0 clock_layer.line_max = 3 clock_layer.line_width = 50 clock_layer.red = 65535 clock_layer.scalable_lines = "true" clock_layer.visible = "true" combine_vertical_logic_groups = "true" command_log_file = "./command.log" company = "" compatibility_version = "v3.2b" compile_assume_fully_decoded_three_state_busses = "false" compile_default_critical_range = 0.000000 compile_disable_area_opt_during_inplace_opt = "false" compile_disable_hierarchical_inverter_opt = "false" compile_dont_touch_annotated_cell_during_inplace_opt = "false" compile_fix_multiple_port_nets = "false" compile_ignore_area_during_inplace_opt = "false" compile_ignore_footprint_during_inplace_opt = "false" compile_implementation_selection = "true" compile_instance_name_prefix = "U" compile_instance_name_suffix = "" compile_negative_logic_methodology = "false" compile_no_new_cells_at_top_level = "false" compile_ok_to_buffer_during_inplace_opt = "false" compile_preserve_sync_resets = "false" compile_update_annotated_delays_during_inplace_opt = "true" compile_use_low_timing_effort = "false" constraint_layer.blue = 0 constraint_layer.green = 0 constraint_layer.line_max = 3 constraint_layer.line_width = 50 constraint_layer.red = 65535 constraint_layer.scalable_lines = "true" constraint_layer.visible = "true" create_clock_no_input_delay = "false" current_design = "<>" current_highlight_layer = "<>" current_instance = "<>" current_reference = "<>" db2sge_bit_type = "std_logic" db2sge_bit_vector_type = "std_logic_vector" db2sge_command = "/opt/digital/synopsys3.2b/sparc/syn/bin/db2sge" db2sge_display_instance_names = "false" db2sge_display_pin_names = "false" db2sge_display_symbol_names = "false" db2sge_one_name = "'1'" db2sge_output_directory = "" db2sge_overwrite = "true" db2sge_scale = "2" db2sge_script = "/opt/digital/synopsys3.2b/admin/setup/.dc_write_sge" db2sge_target_xp = "false" db2sge_tcf_package_file = "synopsys_tcf.vhd" db2sge_unknown_name = "'X'" db2sge_use_bustaps = "false" db2sge_use_compound_names = "true" db2sge_use_lib_section = "" db2sge_zero_name = "'0'" dc_shell_status = 0 default_schematic_options = "-size infinite" design_library_file = ".synopsys_vss.setup" designer = "" designware_layer.blue = 0 designware_layer.green = 0 designware_layer.line_max = 4 designware_layer.line_width = 400 designware_layer.red = 65535 designware_layer.scalable_lines = "true" designware_name_layer.blue = 65535 designware_name_layer.green = 65535 designware_name_layer.red = 65535 designware_name_layer.visible = "true" duplicate_ports = "false" echo_include_commands = "true" edifin_array_range_extraction_style = "" edifin_autoconnect_offpageconnectors = "false" edifin_autoconnect_ports = "false" edifin_dc_script_flag = "" edifin_delete_empty_cells = "true" edifin_delete_ripper_cells = "true" edifin_ground_net_name = "" edifin_ground_net_property_name = "" edifin_ground_net_property_value = "" edifin_ground_port_name = "" edifin_instance_property_name = "" edifin_lib_in_osc_symbol = "" edifin_lib_in_port_symbol = "" edifin_lib_inout_osc_symbol = "" edifin_lib_inout_port_symbol = "" edifin_lib_logic_0_symbol = "" edifin_lib_logic_1_symbol = "" edifin_lib_mentor_netcon_symbol = "" edifin_lib_out_osc_symbol = "" edifin_lib_out_port_symbol = "" edifin_lib_ripper_bits_property = "" edifin_lib_ripper_bus_end = "" edifin_lib_ripper_cell_name = "" edifin_lib_ripper_view_name = "" edifin_lib_route_grid = 1024 edifin_lib_templates = {} edifin_portinstance_disabled_property_name = "" edifin_portinstance_disabled_property_value = "" edifin_portinstance_property_name = "" edifin_power_net_name = "" edifin_power_net_property_name = "" edifin_power_net_property_value = "" edifin_power_port_name = "" edifin_use_identifier_in_rename = "false" edifin_view_identifier_property_name = "" edifout_array_member_naming_style = "" edifout_array_range_naming_style = "" edifout_dc_script_flag = "" edifout_design_name = "Synopsys_edif" edifout_designs_library_name = "DESIGNS" edifout_display_instance_names = "false" edifout_display_net_names = "false" edifout_external = "true" edifout_external_graphic_view_name = "Graphic_representation" edifout_external_netlist_view_name = "Netlist_representation" edifout_external_schematic_view_name = "Schematic_representation" edifout_ground_name = "logic_0" edifout_ground_net_name = "" edifout_ground_net_property_name = "" edifout_ground_net_property_value = "" edifout_ground_pin_name = "logic_0_pin" edifout_ground_port_name = "GND" edifout_instance_property_name = "" edifout_instantiate_ports = "false" edifout_library_graphic_view_name = "Graphic_representation" edifout_library_netlist_view_name = "Netlist_representation" edifout_library_schematic_view_name = "Schematic_representation" edifout_merge_libraries = "false" edifout_multidimension_arrays = "false" edifout_name_oscs_different_from_ports = "false" edifout_name_rippers_same_as_wires = "false" edifout_netlist_only = "false" edifout_no_array = "false" edifout_numerical_array_members = "false" edifout_pin_direction_in_value = "" edifout_pin_direction_inout_value = "" edifout_pin_direction_out_value = "" edifout_pin_direction_property_name = "" edifout_pin_name_property_name = "" edifout_portinstance_disabled_property_name = "" edifout_portinstance_disabled_property_value = "" edifout_portinstance_property_name = "" edifout_power_and_ground_representation = "cell" edifout_power_name = "logic_1" edifout_power_net_name = "" edifout_power_net_property_name = "" edifout_power_net_property_value = "" edifout_power_pin_name = "logic_1_pin" edifout_power_port_name = "VDD" edifout_skip_port_implementations = "false" edifout_target_system = "" edifout_top_level_symbol = "true" edifout_translate_origin = "" edifout_unused_property_value = "" edifout_viewtype_graphic_view_name = "" edifout_viewtype_schematic_view_name = "" edifout_write_attributes = "false" edifout_write_constraints = "false" edifout_write_properties_list = {} enable_page_mode = "true" equationout_and_sign = "*" equationout_or_sign = "+" equationout_postfix_negation = "true" exit_delete_filename_log_file = "true" fast_partitioning = "true" filename_log_file = "filenames.log" filter_check_real_by_default = "true" find_converts_name_lists = "false" font_library = "1_25.font" gen_bus_member_naming_style = "" gen_bus_range_naming_style = "" gen_bussing_exact_implicit = "false" gen_cell_pin_name_separator = "/" gen_create_netlist_busses = "true" gen_dont_show_single_bit_busses = "false" gen_ignore_bus_bit_order = "false" gen_match_ripper_wire_widths = "false" gen_max_compound_name_length = 256 gen_max_ports_on_symbol_side = 0 gen_open_name_postfix = "" gen_open_name_prefix = "Open" gen_show_created_busses = "false" gen_show_created_symbols = "false" gen_single_osc_per_name = "false" generic_symbol_library = "generic.sdb" hdl_keep_licenses = "true" hdl_preferred_license = "" hdlin_auto_save_templates = "FALSE" hdlin_check_no_latch = "FALSE" hdlin_ff_always_async_set_reset = "TRUE" hdlin_ff_always_sync_set_reset = "FALSE" hdlin_files = {} hdlin_keep_feedback = "FALSE" hdlin_keep_inv_feedback = "TRUE" hdlin_latch_always_async_set_reset = "FALSE" hdlin_minimize_tree_delay = "TRUE" hdlin_reg_report_length = 60 hdlin_reg_test_print = "FALSE" hdlin_replace_synthetic = "FALSE" hdlin_report_inferred_modules = "true" hdlin_report_resource_costs = "FALSE" hdlin_resource_allocation = "CONSTRAINT_DRIVEN" hdlin_resource_implementation = "CONSTRAINT_DRIVEN" hdlin_resource_sharing_mode = "AUTOMATIC" hdlin_share_common_subexpressions = "TRUE" hdlin_share_effort = "LOW" hdlin_source_to_gates_mode = "off" hdlin_tdrs_script_source = "" hdlin_translate_off_skip_text = "false" hierarchy_layer.blue = 0 hierarchy_layer.green = 65535 hierarchy_layer.line_width = 2 hierarchy_layer.red = 65535 hierarchy_layer.scalable_lines = "false" hierarchy_layer.visible = "true" hierarchy_name_layer.blue = 65535 hierarchy_name_layer.green = 65535 hierarchy_name_layer.red = 65535 hierarchy_name_layer.visible = "true" highlight_layer0.blue = 0 highlight_layer0.green = 0 highlight_layer0.line_width = 5 highlight_layer0.plot_line_width = 10 highlight_layer0.red = 65535 highlight_layer0.scalable_lines = "false" highlight_layer0.visible = "true" highlight_layer1.blue = 0 highlight_layer1.green = 65535 highlight_layer1.line_width = 5 highlight_layer1.plot_line_width = 10 highlight_layer1.red = 0 highlight_layer1.scalable_lines = "false" highlight_layer1.visible = "true" highlight_layer2.blue = 65535 highlight_layer2.green = 0 highlight_layer2.line_width = 5 highlight_layer2.plot_line_width = 10 highlight_layer2.red = 65535 highlight_layer2.scalable_lines = "false" highlight_layer2.visible = "true" highlight_layer3.blue = 35389 highlight_layer3.green = 50462 highlight_layer3.line_width = 5 highlight_layer3.plot_line_width = 10 highlight_layer3.red = 65535 highlight_layer3.scalable_lines = "false" highlight_layer3.visible = "true" highlight_layer4.blue = 0 highlight_layer4.green = 65535 highlight_layer4.line_width = 5 highlight_layer4.plot_line_width = 10 highlight_layer4.red = 62258 highlight_layer4.scalable_lines = "false" highlight_layer4.visible = "true" hlo_ignore_priorities = "false" hlo_minimize_tree_delay = "true" hlo_resource_allocation = "constraint_driven" hlo_resource_implementation = "constraint_driven" hlo_share_common_subexpressions = "true" hlo_share_effort = "low" init_path = "/opt/digital/synopsys3.2b/aux/syn" insert_test_design_naming_style = "%s_test_%d" isatty = 0 jtag_manufacturer_id = 0 jtag_part_number = 65535 jtag_port_drive_limit = 6 jtag_test_clock_port_naming_style = "jtag_tck%s" jtag_test_data_in_port_naming_style = "jtag_tdi%s" jtag_test_data_out_port_naming_style = "jtag_tdo%s" jtag_test_mode_select_port_naming_style = "jtag_tms%s" jtag_test_reset_port_naming_style = "jtag_trst%s" jtag_version_number = 0 left_justify_logic_constants = "false" level_sensitive_startpoint_close_active_edge = 0 link_force_case = "check_reference" link_library = {"*", "your_library.db"} link_path = {"*", "your_library.db"} logic_group_height_percent = 95 logic_group_width_percent = 95 lsiin_net_name_prefix = "NET_" lsiout_inverter_cell = "" lsiout_upcase = "true" man_path = "/opt/digital/synopsys3.2b/doc/syn/man" mentor_bidirect_value = "INOUT" mentor_do_path = "" mentor_input_output_property_name = "PINTYPE" mentor_input_value = "IN" mentor_logic_one_value = "1SF" mentor_logic_zero_one_property_name = "INIT" mentor_logic_zero_value = "0SF" mentor_output_value = "OUT" mentor_primitive_property_name = "PRIMITIVE" mentor_primitive_property_value = "MODULE" mentor_reference_property_name = "COMP" mentor_search_path = "" mentor_write_symbols = "true" motif_files = "/opt/digital/synopsys3.2b/admin/setup" motorola_input_edge_rate = 0.000000 multi_pass_test_generation = "false" net_layer.blue = 65535 net_layer.green = 65535 net_layer.line_width = 1 net_layer.red = 0 net_layer.scalable_lines = "false" net_layer.visible = "true" net_name_layer.blue = 65535 net_name_layer.green = 65535 net_name_layer.red = 65535 net_name_layer.visible = "false" osc_layer.blue = 0 osc_layer.green = 65535 osc_layer.line_max = 2 osc_layer.line_width = 200 osc_layer.red = 65535 osc_layer.scalable_lines = "true" osc_layer.visible = "true" osc_name_layer.blue = 65535 osc_name_layer.green = 65535 osc_name_layer.red = 65535 osc_name_layer.visible = "true" output_order = {} pin_name_layer.blue = 65535 pin_name_layer.green = 65535 pin_name_layer.red = 65535 pin_name_layer.visible = "false" pla_read_create_flip_flop = "false" plot_box = "false" plot_command = "lpr -Plw" plot_orientation = "best_fit" plot_scale_factor = 100 plotter_maxx = 584 plotter_maxy = 764 plotter_minx = 28 plotter_miny = 28 port_complement_naming_style = "%s_BAR" port_edge_rate = 0.000000 port_layer.blue = 0 port_layer.green = 65535 port_layer.line_max = 2 port_layer.line_width = 200 port_layer.red = 65535 port_layer.scalable_lines = "true" port_layer.visible = "true" port_name_layer.blue = 65535 port_name_layer.green = 65535 port_name_layer.red = 65535 port_name_layer.visible = "true" power_keep_license_after_power_commands = "false" preserve_subshells = {"hdl_shell_exec"} product_build_date = "Jan 27, 1995" product_version = "v3.2b" read_array_minus_style = "" read_array_naming_style = "" read_array_separator_style = "" read_cell_transition = "true" read_inferred_bus_naming_style = "" read_net_transition = "false" reoptimize_design_changed_list_file_name = "" report_product_version = "" ripper_pin_name_layer.blue = 65535 ripper_pin_name_layer.green = 65535 ripper_pin_name_layer.red = 65535 ripper_pin_name_layer.visible = "false" sdfin_fall_cell_delay_type = "maximum" sdfin_fall_net_delay_type = "maximum" sdfin_min_fall_cell_delay = 0.000000 sdfin_min_fall_net_delay = 0.000000 sdfin_min_rise_cell_delay = 0.000000 sdfin_min_rise_net_delay = 0.000000 sdfin_rise_cell_delay_type = "maximum" sdfin_rise_net_delay_type = "maximum" sdfin_top_instance_name = "" sdfout_allow_non_positive_constraints = "false" sdfout_min_fall_cell_delay = 0.000000 sdfout_min_fall_net_delay = 0.000000 sdfout_min_rise_cell_delay = 0.000000 sdfout_min_rise_net_delay = 0.000000 sdfout_time_scale = 1.000000 sdfout_top_instance_name = "" sdfout_write_to_output = "false" search_path = {".", "/opt/digital/synopsys3.2b/libraries/syn"} sheet_fill_percent = 100 sheet_hard_limit = "true" sheet_orientation = "landscape" sheet_size = "infinite" sheet_sizes = "{A, B, C, D, E, infinite, mentor_maximum, sge_maximum}" shell_prompt = "design_analyzer> " single_group_per_sheet = "false" sort_outputs = "false" suppress_errors = {} symbol_layer.blue = 0 symbol_layer.green = 65535 symbol_layer.line_max = 3 symbol_layer.line_width = 200 symbol_layer.red = 65535 symbol_layer.scalable_lines = "true" symbol_layer.visible = "true" symbol_library = {"your_library.sdb"} symbol_name_layer.blue = 65535 symbol_name_layer.green = 65535 symbol_name_layer.red = 65535 symbol_name_layer.visible = "true" synlib_disable_limited_licenses = "true" synlib_dont_get_license = {} synlib_evaluation_mode = "false" synlib_model_map_effort = "medium" synlib_optimize_non_cache_elements = "true" synopsys_program_name = "design_analyzer" synopsys_root = "/opt/digital/synopsys3.2b" synthetic_library = {} target_library = {"your_library.db"} target_systems = {} tdlout_upcase = "true" template_layer.blue = 45875 template_layer.green = 45875 template_layer.line_width = 3 template_layer.red = 0 template_layer.scalable_lines = "false" template_layer.visible = "true" template_naming_style = "%s_%p" template_parameter_style = "%s%d" template_separator_style = "_" template_text_layer.blue = 65535 template_text_layer.green = 65535 template_text_layer.red = 65535 template_text_layer.visible = "true" test_clock_port_naming_style = "test_c%s" test_default_bidir_delay = 55.000000 test_default_delay = 5.000000 test_default_min_fault_coverage = 95 test_default_period = 100.000000 test_default_strobe = 95.000000 test_default_strobe_width = 0.000000 test_non_scan_clock_port_naming_style = "test_nsc_%s" test_scan_clock_a_port_naming_style = "test_sca%s" test_scan_clock_b_port_naming_style = "test_scb%s" test_scan_clock_port_naming_style = "test_sc%s" test_scan_enable_inverted_port_naming_style = "test_sei%s" test_scan_enable_port_naming_style = "test_se%s" test_scan_in_port_naming_style = "test_si%s%s" test_scan_out_port_naming_style = "test_so%s%s" text_change_select_region_mode = "basic" text_editor_command = "xterm -fn 8x13 -e vi %s &" text_print_command = "lpr -Plw" text_threshold = 6 text_unselect_on_button_press = "true" timing_self_loops_no_skew = "false" true_delay_prove_false_backtrack_limit = 1000 true_delay_prove_true_backtrack_limit = 1000 uniquify_naming_style = "%s_%d" use_port_name_for_oscs = "true" user_home_path = "/home/ugrad5/sharring" variable_layer.visible = "false" verbose_messages = "true" verilogout_equation = "false" verilogout_higher_designs_first = "FALSE" verilogout_ignore_case = "false" verilogout_no_tri = "false" verilogout_single_bit = "false" verilogout_time_scale = 1.000000 verilogout_top_instance_name = "u1" vhdllib_architecture = {"FTBM", "UDSM", "FTSM", "FTGS", "VITAL"} vhdllib_glitch_handle = "true" vhdllib_logic_system = "ieee-1164" vhdllib_logical_name = "" vhdllib_pulse_handle = "use_vhdllib_glitch_handle" vhdllib_tb_compare = 0 vhdllib_tb_x_eq_dontcare = "FALSE" vhdllib_timing_checks = "true" vhdllib_timing_mesg = "true" vhdllib_timing_xgen = "false" vhdlout_architecture_name = "SYN_%a_%u" vhdlout_bit_type = "std_logic" vhdlout_bit_type_resolved = "TRUE" vhdlout_bit_vector_type = "std_logic_vector" vhdlout_conversion_functions = {} vhdlout_dont_write_types = "FALSE" vhdlout_equations = "FALSE" vhdlout_one_name = "'1'" vhdlout_package_naming_style = "CONV_PACK_%d" vhdlout_preserve_hierarchical_types = "VECTOR" vhdlout_separate_scan_in = "FALSE" vhdlout_single_bit = "USER" vhdlout_target_simulator = "" vhdlout_three_state_name = "'Z'" vhdlout_three_state_res_func = "" vhdlout_time_scale = 1.000000 vhdlout_top_configuration_arch_name = "A" vhdlout_top_configuration_entity_name = "E" vhdlout_top_configuration_name = "CFG_TB_E" vhdlout_unknown_name = "'X'" vhdlout_upcase = "FALSE" vhdlout_use_packages = {"IEEE.std_logic_1164"} vhdlout_wired_and_res_func = "" vhdlout_wired_or_res_func = "" vhdlout_write_architecture = "TRUE" vhdlout_write_components = "TRUE" vhdlout_write_entity = "TRUE" vhdlout_write_top_configuration = "FALSE" vhdlout_zero_name = "'0'" view_analyze_file_suffix = {"v", "vhd", "vhdl"} view_arch_types = {"apollo", "decmips", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"} view_background = "black" view_banner_font = "9x15" view_busy_during_selection = "true" view_cache_images = "true" view_clear_whole_area_on_delete = "false" view_command_log_file = "./view_command.log" view_command_win_max_lines = 1000 view_dialogs_modal = "true" view_disable_cursor_warping = "true" view_disable_error_windows = "false" view_disable_output = "false" view_draw_text_breakpoint = 0.010000 view_error_window_count = 6 view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"} view_extend_thick_lines = "true" view_icon_font = "8x13" view_icon_path = "/opt/digital/synopsys3.2b/aux/syn/icons" view_image_cache_options = 1 view_independent_dialogs = "{test_report, Test Reports , report_print, Report , report_options, Report Options , report_win, Report Output , manual_page, Manual Page }" view_linear_box_search_percentage = 95 view_linear_line_search_percentage = 85 view_log_file = "" view_max_image_size_to_cache = 175 view_maximum_route_grids = 0 view_on_line_doc_cmd = "/opt/digital/synopsys3.2b/iview1/bin/iview" view_pixels_per_route_grid = 0 view_read_file_suffix = {"db", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"} view_script_submenu_items = {"DA to SGE Transfer", "write_sge"} view_select_default_message = "Left Button: Select - Middle Button: Add/Modify Select - Right Button: Menu" view_select_separator = " - " view_set_cursor_area = 5 view_set_draw_interrupt_limit = 500 view_set_select_interrupt_limit = 200 view_set_selecting_color = "" view_tools_menu_items = {} view_use_integer_scaling = "false" view_use_small_cursor = "" view_use_x_routines = "true" view_watcher = "/opt/digital/synopsys3.2b/sparc/syn/bin/da_watcher_exec" view_win_height = 500 view_win_width = 600 view_write_file_suffix = {"db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"} working_path = "/amd/lincoln/amd/lincoln/ugrad5/sharring/tutorial/lfsr_syn" write_cell_transition = "true" write_name_nets_same_as_ports = "false" write_net_transition = "false" write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"} write_test_include_scan_cell_info = "true" write_test_input_dont_care_value = "X" write_test_max_cycles = 0 write_test_max_scan_patterns = 0 write_test_pattern_set_naming_style = "TC_Syn_%d" write_test_scan_check_file_naming_style = "%s_schk.%s" write_test_vector_file_naming_style = "%s_%d.%s" x11_display_string = "dsil10:0.0" x11_is_color = "true" x11_set_cursor_background = "" x11_set_cursor_foreground = "" x11_set_cursor_number = "-1" x11_vendor_release_number = 5000 x11_vendor_string = "MIT X C" x11_vendor_version_number = 11 xnfin_dff_clock_enable_pin_name = "CE" xnfin_dff_clock_pin_name = "C" xnfin_dff_data_pin_name = "D" xnfin_dff_q_pin_name = "Q" xnfin_dff_reset_pin_name = "RD" xnfin_dff_set_pin_name = "SD" xnfin_family = "4000" xnfin_ignore_pins = "GTS GSR GR" xnfout_clock_attribute_style = "CLK_ONLY" xnfout_constraints_per_endpoint = "50" xnfout_default_time_constraints = "true" xnfout_library_version = "" /* Initial design_analyzer Aliases */ alias check_clocks "check_timing" alias compile_inplace_changed_list_file_name "reoptimize_design_changed_list_file_name" alias compile_test "insert_test" alias create_test_vectors "create_test_patterns" alias disable_timing "set_disable_timing" alias dont_touch "set_dont_touch" alias dont_touch_network "set_dont_touch_network" alias dont_use "set_dont_use" alias fix_hold "set_fix_hold" alias free "remove_design" alias fsm_minimize "minimize_fsm" alias fsm_reduce "reduce_fsm" alias gen "create_schematic" alias group_bus "create_bus" alias groupvar "group_variable" alias lint "check_design" alias ls "sh ls -aC" alias man "help" alias prefer "set_prefer" alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" alias report_attributes "report_attribute" alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" alias report_clock_tree "report_transitive_fanout -clock_tree" alias report_clocks "report_clock" alias report_constraints "report_constraint" alias report_register "report_timing_requirements;report_clock -skew" alias report_synthetic "report_cell" alias set_connect_delay "set_annotated_delay -net" alias set_internal_arrival "set_arrival" alias set_internal_load "set_load" alias ungroup_bus "remove_bus" alias verify "compare_design" alias view_cursor_number "x11_set_cursor_number" alias write_sge "include db2sge_script" /* design_analyzer Command Log */ read -format db {"/amd/lincoln/amd/lincoln/ugrad5/sharring/tutorial/lfsr_syn/lfsr.db"} create_schematic -size infinite -gen_database create_schematic -size infinite -symbol_view create_schematic -size infinite -hier_view create_schematic -size infinite -schematic_view highlight_path -critical_path