/* lfsr.dcsh
** dc_shell script for LFSR Counter example project
** Target device Xilinx 3042PC84-50

search_path = {. \
	/opt/digital/share/xilinx3/xact/synopsys/libraries/syn \
	/opt/digital/synopsys3.2b/libraries/syn}

link_library = {xprim_3042-50.db xprim_3000-50.db \
	xgen_3000.db xdc_3000-50.db}

target_library = {xprim_3042-50.db xprim_3000-50.db \
	xgen_3000.db xdc_3000-50.db}

symbol_library = xc3000.sdb

define_design_lib WORK -path ./WORK

compile_fix_multiple_port_nets = true

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number port_location part"

designer = "Scott Harrington"
company = "Duke EE"
TOP = "lfsr"

/* read -format vhdl pointers.vhd
** read -format vhdl natasha.vhd
*/

/* analyze -format vhdl {this_project_has.vhd multiple_modules.vhd} */

analyze -format vhdl lfsr.vhd
elaborate TOP

current_design TOP

set_operating_conditions WCCOM
set_wire_load "3042-50_avg"
set_port_is_pad "*"
set_pad_type -slewrate high all_outputs()

/* Insert the FPGA pads before compile so that logic can be mapped
** into IOBs
*/
insert_pads 

remove_constraint -all

create_clock "Clk" -period 100
uniquify 

compile -ungroup_all -boundary_optimization 

report_area > TOP + ".area"
report_timing > TOP + ".timing"

set_attribute TOP "part" -type string "3042pc84-50"
/* set_attribute {Z} "pad_location" -type string "P70"
** set_attribute find(design lfsr) "xnfout_use_blknames" -type boolean FALSE
** set_attribute find(design lfsr) "xnfout_write_map_symbols" -type boolean FALSE
*/

write -format db -hierarchy -output TOP + ".db"

/* replace_fpga */

xnfout_library_version = "5.0.0"
write -format edif -hierarchy -output TOP + ".sedif"
/* write -format xnf -hierarchy -output TOP + ".sxnf" */

exit