XMAKE Version 5.1.0 Copyright (c) 1989-1994 Xilinx Inc. All rights reserved XMAKE: Generating makefile 'lfsr.mak'... XMAKE: Set the part type to '3042PC84-50' from the command line, overriding the part type specified in the design, if any. XMAKE: Profile used is 'xdm.pro'. XMAKE: Execute command 'syn2xnf -force -parttype 3042PC84-50 lfsr.sedif'. ****************************************************************************** >>> SYN2XNF '-force' option is always selected by XMAKE. ************************************************************************** SYN2XNF Version 3.5.0 (c) Copyright 1992, 1993, 1994 Xilinx Inc. All rights reserved. Converting lfsr.sedif to XNF ... INFO: Using part type 3042PC84-50 EDIF2XNF (EDIF2VERILOG) Version 5.1.0b Copyright (c) 1991-1994 Xilinx Inc. Reading EDIF netlist file lfsr.sedif ... Writing temporary file ... XNFMERGE Ver. 5.1.0 (c) Copyright 1987-1994 Xilinx Inc. All rights reserved List of files read Read temporary file Read file /opt/digital/share/xilinx3/xact/data/synopsys/xprim_3000/fdce.xnf Read file /opt/digital/share/xilinx3/xact/data/synopsys/xprim_3000/bufg_f.xnf Read file /opt/digital/share/xilinx3/xact/data/synopsys/xprim_3000/xnor2.xnf Netlist written to file lfsr.xff XMAKE: Running with the following XMAKE options: -P 3042PC84-50 XMAKE: Makefile saved in 'lfsr.mak'. XMAKE: Making 'lfsr.bit'... XMAKE: Execute command 'xnfprep lfsr.xff lfsr.xtf parttype=3042PC84-50'. ****************************************************************************** xnfprep [5.1.0] -- Xilinx Automatic CAE Tools Copyright (c) 1995 Xilinx Inc. All Rights Reserved. + xnfprep @ 1995/04/09 17:24:40 [00:00:03] + Parameters ----------------------- design = lfsr.xff outfile = lfsr.xtf report = *** savesig = FALSE parttype = 3042PC84-50 cstfile = *** logfile = xnfprep.log ----------------------- xnfprep: running design rule checker ... xnfprep: trimming unnecessary and redundant logic... xnfprep: running design rule checker on trimmed design... XNFPREP SUMMARY --------------- 0 Errors found 1 Warnings found 0 Unnecessary inverters and buffers removed 0 Unnecessary or disabled symbols removed 0 Sourceless or loadless signals removed Refer to the lfsr.prp file for details. Output netlist written to file lfsr.xtf. - xnfprep @ 1995/04/09 17:24:46 [00:00:07] = -------- @ 1995/04/09 00:00:06 [00:00:04] + xnfprep required [878.929] Kbytes of dynamic/allocated memory + Data Manager Auto Save Saving MAP_XNF_TRIM cell "lfsr" - Data Manager Auto Save XMAKE: Execute command 'xnfmap -P 3042PC84-50 lfsr.xtf lfsr.map'. ****************************************************************************** XNFMAP Ver. 5.1.0 (c) Copyright 1987-1994 Xilinx Inc. All rights reserved Reading file lfsr.xtf... Checking network for logical errors... Preparing design... Assigning logic to LCA elements... Preparing GUIDE file... Checking mapped logic blocks... DESIGN SUMMARY: Part type=3042PC84-50 3 of 144 CLBs used 6 of 74 I/O pins used 0 of 22 internal IOBs used 0 of 24 internal three-state signals used (0 TBUFS used) 4 CLB flipflops used Total number of WARNINGS generated during mapping = 0. Total number of ERRORS generated during mapping = 0. Writing design file lfsr.map... WARNING 356: The following IOBs could not be named using the IO pad name, since that name conflicts with a reserved LCA name or was used as a name for another block. These IO signals will appear in APR, PPR, and XDELAY reports with the alternate IOB names shown below. PAD = CE IOB Name = N39<0> Writing guide file lfsr.pgf... XMAKE: Execute command 'map2lca -P 3042PC84-50 lfsr.map lfsr.lca'. ****************************************************************************** MAP2LCA Ver. 5.0.0 (c) Copyright 1988-1994 Xilinx Inc. All rights reserved Checking network for logical errors... Assigning logic to LCA elements... SUMMARY: Part type=3042PC84-50 3 of 144 CLBs used 6 of 74 I/O pins used 0 of 22 internal IOBs used 0 of 24 internal three-state signals used Design written to file lfsr.lca (APR constraints in lfsr.scp) XMAKE: Execute command 'apr -W -Y lfsr.lca lfsr.lca'. ****************************************************************************** AUTOMATIC PLACE AND ROUTE PROGRAM -- Version 5.0.0 Copyright (C) 1986-1994 by Xilinx, Inc. All Rights Reserved. Sun Apr 9 17:24:54 1995 Input Design File: lfsr.lca Part Type: 3042PC84 Speed Grade: -50 Guide Design File: (none) Schematic File: lfsr.scp Constraints File: (none) Options: -a3 -r4 -s6246 -w -y Output Design File: lfsr.lca Report File: lfsr.rpt Message File: (none) Reading input design... Reading constraints... Placing blocks... Initial score: *425* Annealing... Estimated execution time for placement: 00:00:00 -------------------------------------------------------------------- Best % of Avg Placement Temp %Chng Score Init Score %Chng Stdev CPU time -------------------------------------------------------------------- 4614.5 **** 1520 358% 2015 ***** 12.9% 00:00:00 4580.1 -1% 1520 358% 2317 15.0% 16.4% 00:00:00 4502.6 -2% 1190 280% 1908 -17.7% 19.0% 00:00:00 4409.3 -2% 1160 273% 2175 14.0% 19.2% 00:00:00 4294.3 -3% 1160 273% 2272 4.5% 13.8% 00:00:00 4175.2 -3% 1160 273% 2111 -7.1% 9.1% 00:00:00 4034.0 -3% 1160 273% 2151 1.9% 16.6% 00:00:00 3837.8 -5% 1160 273% 2055 -4.5% 13.6% 00:00:00 3646.8 -5% 1160 273% 2235 8.7% 15.4% 00:00:00 3456.1 -5% 1160 273% 2267 1.5% 13.8% 00:00:00 3281.1 -5% 1160 273% 2245 -1.0% 15.2% 00:00:00 3073.3 -6% 1160 273% 2194 -2.3% 14.9% 00:00:00 2870.0 -7% 1160 273% 2197 0.1% 13.6% 00:00:00 2685.3 -6% 945 222% 2075 -5.6% 16.7% 00:00:00 2502.5 -7% 945 222% 2057 -0.9% 13.6% 00:00:00 2344.0 -6% 945 222% 2129 3.5% 17.2% 00:00:00 -------------------------------------------------------------------- Best % of Avg Placement Temp %Chng Score Init Score %Chng Stdev CPU time -------------------------------------------------------------------- 2158.2 -8% 945 222% 2234 4.9% 13.6% 00:00:00 1999.3 -7% 945 222% 2182 -2.3% 12.8% 00:00:00 1846.5 -8% 945 222% 2156 -1.2% 12.9% 00:00:00 1703.6 -8% 945 222% 2057 -4.6% 19.7% 00:00:00 1549.7 -9% 945 222% 2014 -2.1% 17.8% 00:00:00 1409.8 -9% 945 222% 2043 1.4% 13.1% 00:00:01 1286.4 -9% 945 222% 1969 -3.6% 15.0% 00:00:01 1178.1 -8% 945 222% 2076 5.5% 14.1% 00:00:01 1073.9 -9% 945 222% 2042 -1.7% 16.0% 00:00:01 967.2 -10% 945 222% 2001 -2.0% 12.8% 00:00:01 869.3 -10% 945 222% 1784 -10.9% 14.9% 00:00:01 784.1 -10% 830 195% 1700 -4.7% 20.1% 00:00:01 708.5 -10% 830 195% 2081 22.4% 10.9% 00:00:01 634.3 -10% 830 195% 2077 -0.2% 17.0% 00:00:01 569.6 -10% 830 195% 1838 -11.5% 11.2% 00:00:01 509.8 -10% 830 195% 2062 12.2% 12.3% 00:00:01 -------------------------------------------------------------------- Best % of Avg Placement Temp %Chng Score Init Score %Chng Stdev CPU time -------------------------------------------------------------------- 453.7 -11% 830 195% 2020 -2.0% 16.1% 00:00:01 403.7 -11% 830 195% 1819 -9.9% 10.5% 00:00:01 356.7 -12% 830 195% 1799 -1.1% 7.8% 00:00:01 314.3 -12% 830 195% 2237 24.4% 9.8% 00:00:01 277.9 -12% 830 195% 1727 -22.8% 8.3% 00:00:01 245.1 -12% 830 195% 1601 -7.3% 11.1% 00:00:01 214.9 -12% 830 195% 1569 -2.0% 8.3% 00:00:02 188.9 -12% 830 195% 1676 6.8% 10.9% 00:00:02 165.6 -12% 830 195% 1694 1.1% 18.5% 00:00:02 145.1 -12% 830 195% 1895 11.9% 8.7% 00:00:02 126.6 -13% 830 195% 1704 -10.1% 9.0% 00:00:02 108.3 -14% 830 195% 1349 -20.8% 18.2% 00:00:02 96.6 -11% 785 185% 1165 -13.7% 13.1% 00:00:02 86.0 -11% 785 185% 1336 14.7% 15.3% 00:00:02 77.6 -10% 785 185% 1297 -2.9% 14.7% 00:00:02 68.7 -12% 785 185% 1353 4.3% 14.5% 00:00:02 -------------------------------------------------------------------- Best % of Avg Placement Temp %Chng Score Init Score %Chng Stdev CPU time -------------------------------------------------------------------- 58.2 -15% 785 185% 1425 5.3% 14.9% 00:00:03 51.0 -12% 785 185% 1236 -13.3% 6.4% 00:00:03 46.5 -9% 785 185% 1108 -10.3% 7.8% 00:00:03 42.8 -8% 785 185% 995 -10.2% 6.2% 00:00:03 38.0 -11% 754 177% 982 -1.3% 12.4% 00:00:03 34.8 -9% 709 167% 841 -14.3% 7.0% 00:00:03 30.5 -12% 709 167% 932 10.9% 8.0% 00:00:03 27.6 -10% 687 162% 818 -12.2% 10.3% 00:00:03 25.3 -8% 687 162% 781 -4.6% 6.9% 00:00:03 22.8 -10% 680 160% 757 -3.1% 7.2% 00:00:04 21.4 -6% 680 160% 765 1.1% 6.4% 00:00:04 19.9 -7% 680 160% 757 -1.1% 6.8% 00:00:04 18.1 -9% 680 160% 752 -0.6% 5.1% 00:00:04 17.1 -6% 642 151% 759 0.9% 11.6% 00:00:04 15.7 -8% 642 151% 712 -6.2% 6.2% 00:00:04 14.9 -5% 642 151% 665 -6.6% 2.6% 00:00:04 -------------------------------------------------------------------- Best % of Avg Placement Temp %Chng Score Init Score %Chng Stdev CPU time -------------------------------------------------------------------- 14.1 -6% 642 151% 663 -0.2% 2.4% 00:00:04 Quenching... 0.0 **** 642 151% 642 -3.2% 0.0% 00:00:05 0.0 **** 642 151% 642 0.0% 0.0% 00:00:05 0.0 **** 642 151% 642 0.0% 0.0% 00:00:05 Final score: *642* Total Placement CPU time: 00:00:05 Adopting new placement... Writing placed but unrouted design... Assigning long lines... Routing nets... Iteration 1... Using delay-driven detail router... Detail Routing (with Rip-up & Retry Routing)... Percent nets scanned: ..20%..30%..50%..60%..70%..90%..100% Rip-up & Retry Routing and Routing Improvement on 0 unrouted load pins in unwritten design... Percent nets scanned: ..20%..30%..50%..60%..70%..90%..100% There are 0 unrouted load pins. Routing CPU time: 00:00:02 Writing new design... Placement Improvement... Using delay-driven detail router... Percent blks scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100% There are 0 unrouted load pins. Routing CPU time: 00:00:05 Writing new design... Timing Improvement... Using delay-driven detail router... Exhaustive Rip-up Retry... Percent nets scanned: ..20%..30%..50%..60%..70%..90%..100% There are 0 unrouted load pins. Total Routing CPU time: 00:00:06 Checking results... Timing nets... Writing report... Writing new design... Total elapsed time: 0 hrs, 0 mins, 16 secs There are 0 unrouted load pins. Done. Sun Apr 9 17:25:09 1995 XMAKE: Execute command 'makebits -B -R2 -S0 -T -XB -YA lfsr.lca'. ****************************************************************************** Xilinx LCA MAKEBITS Ver. 5.0.0 Copyright 1985-1994 Xilinx Inc. All Rights Reserved. Loading die/package file... Loading design file... Timing nets... Tie to unused sources.. Tie to used sources.. Tie to pin KI.X, net Q38<3> Tie to pin KH.X, net Q38<2> Net Q38<2>: programming: 230 59 Tie to pin KH.Y, net Q38<1> Net Q38<1>: programming: 228 74 Net Q38<1>: programming: 212 88 Net Q38<1>: programming: 212 105 Net Q38<1>: programming: 212 118 Net Q38<1>: programming: 212 135 Net Q38<1>: programming: 212 148 Net Q38<1>: programming: 212 165 Net Q38<1>: programming: 212 178 Net Q38<1>: programming: 212 195 Net Q38<1>: programming: 212 208 Net Q38<1>: programming: 212 225 Net Q38<1>: programming: 212 238 Net Q38<1>: programming: 212 255 Net Q38<1>: programming: 212 268 Net Q38<1>: programming: 212 285 Net Q38<1>: programming: 212 298 Net Q38<1>: programming: 212 315 Net Q38<1>: programming: 212 328 Net Q38<1>: programming: 212 345 Net Q38<1>: programming: 212 358 Net Q38<1>: programming: 212 372 Net Q38<1>: programming: 212 75 Net Q38<1>: programming: 212 58 Net Q38<1>: programming: 212 45 Net Q38<1>: programming: 212 25 Tie to pin LH.Y, net N78 Tie to pin P45.I, net N39<0> Net N39<0>: programming: 202 44 Net N39<0>: programming: 205 45 Net N39<0>: programming: 231 75 Tie to clocks.. TIE_ACLK_O: adding pin ACLK.O Tie to pin ACLK.O, net TIE_ACLK_O Tie to pin GCLK.O, net N68 Net N68: programming: 29 374 54 374 80 374 106 374 132 374 158 374 184 374 262 374 288 374 314 374 Tie to other pins.. TIE_P73_Q: adding pin P73.Q Tie to pin P73.Q, net TIE_P73_Q TIE_P72_Q: adding pin P72.Q Tie to pin P72.Q, net TIE_P72_Q TIE_U27_Q: adding pin U27.Q Tie to pin U27.Q, net TIE_U27_Q TIE_U28_Q: adding pin U28.Q Tie to pin U28.Q, net TIE_U28_Q TIE_P71_Q: adding pin P71.Q Tie to pin P71.Q, net TIE_P71_Q TIE_P70_Q: adding pin P70.Q Tie to pin P70.Q, net TIE_P70_Q TIE_U31_Q: adding pin U31.Q Tie to pin U31.Q, net TIE_U31_Q TIE_P69_Q: adding pin P69.Q Tie to pin P69.Q, net TIE_P69_Q TIE_P68_Q: adding pin P68.Q Tie to pin P68.Q, net TIE_P68_Q TIE_P67_Q: adding pin P67.Q Tie to pin P67.Q, net TIE_P67_Q TIE_P66_Q: adding pin P66.Q Tie to pin P66.Q, net TIE_P66_Q TIE_P65_Q: adding pin P65.Q Tie to pin P65.Q, net TIE_P65_Q TIE_P63_Q: adding pin P63.Q Tie to pin P63.Q, net TIE_P63_Q TIE_P62_Q: adding pin P62.Q Tie to pin P62.Q, net TIE_P62_Q TIE_P61_Q: adding pin P61.Q Tie to pin P61.Q, net TIE_P61_Q TIE_P60_Q: adding pin P60.Q Tie to pin P60.Q, net TIE_P60_Q TIE_U41_Q: adding pin U41.Q Tie to pin U41.Q, net TIE_U41_Q TIE_P59_Q: adding pin P59.Q Tie to pin P59.Q, net TIE_P59_Q TIE_U43_Q: adding pin U43.Q Tie to pin U43.Q, net TIE_U43_Q TIE_P58_Q: adding pin P58.Q Tie to pin P58.Q, net TIE_P58_Q TIE_U45_Q: adding pin U45.Q Tie to pin U45.Q, net TIE_U45_Q TIE_U46_Q: adding pin U46.Q Tie to pin U46.Q, net TIE_U46_Q TIE_P57_Q: adding pin P57.Q Tie to pin P57.Q, net TIE_P57_Q TIE_P56_Q: adding pin P56.Q Tie to pin P56.Q, net TIE_P56_Q TIE_P75_Q: adding pin P75.Q Tie to pin P75.Q, net TIE_P75_Q TIE_P53_Q: adding pin P53.Q Tie to pin P53.Q, net TIE_P53_Q TIE_P76_Q: adding pin P76.Q Tie to pin P76.Q, net TIE_P76_Q TIE_P52_Q: adding pin P52.Q Tie to pin P52.Q, net TIE_P52_Q TIE_U22_Q: adding pin U22.Q Tie to pin U22.Q, net TIE_U22_Q TIE_P51_Q: adding pin P51.Q Tie to pin P51.Q, net TIE_P51_Q TIE_U21_Q: adding pin U21.Q Tie to pin U21.Q, net TIE_U21_Q TIE_P50_Q: adding pin P50.Q Tie to pin P50.Q, net TIE_P50_Q TIE_P77_Q: adding pin P77.Q Tie to pin P77.Q, net TIE_P77_Q TIE_U53_Q: adding pin U53.Q Tie to pin U53.Q, net TIE_U53_Q TIE_P78_Q: adding pin P78.Q Tie to pin P78.Q, net TIE_P78_Q TIE_U54_Q: adding pin U54.Q Tie to pin U54.Q, net TIE_U54_Q TIE_P79_Q: adding pin P79.Q Tie to pin P79.Q, net TIE_P79_Q TIE_P49_Q: adding pin P49.Q Tie to pin P49.Q, net TIE_P49_Q TIE_P80_Q: adding pin P80.Q Tie to pin P80.Q, net TIE_P80_Q TIE_P48_Q: adding pin P48.Q Tie to pin P48.Q, net TIE_P48_Q TIE_P81_Q: adding pin P81.Q Tie to pin P81.Q, net TIE_P81_Q TIE_P47_Q: adding pin P47.Q Tie to pin P47.Q, net TIE_P47_Q TIE_P82_Q: adding pin P82.Q Tie to pin P82.Q, net TIE_P82_Q TIE_P46_Q: adding pin P46.Q Tie to pin P46.Q, net TIE_P46_Q TIE_P83_Q: adding pin P83.Q Tie to pin P83.Q, net TIE_P83_Q TIE_P45_Q: adding pin P45.Q Tie to pin P45.Q, net TIE_P45_Q TIE_P84_Q: adding pin P84.Q Tie to pin P84.Q, net TIE_P84_Q TIE_P44_Q: adding pin P44.Q Tie to pin P44.Q, net TIE_P44_Q TIE_P2_Q: adding pin P2.Q Tie to pin P2.Q, net TIE_P2_Q TIE_P42_Q: adding pin P42.Q Tie to pin P42.Q, net TIE_P42_Q TIE_P3_Q: adding pin P3.Q Tie to pin P3.Q, net TIE_P3_Q TIE_P41_Q: adding pin P41.Q Tie to pin P41.Q, net TIE_P41_Q TIE_P4_Q: adding pin P4.Q Tie to pin P4.Q, net TIE_P4_Q TIE_P40_Q: adding pin P40.Q Tie to pin P40.Q, net TIE_P40_Q TIE_P5_Q: adding pin P5.Q Tie to pin P5.Q, net TIE_P5_Q TIE_P39_Q: adding pin P39.Q Tie to pin P39.Q, net TIE_P39_Q TIE_P6_Q: adding pin P6.Q Tie to pin P6.Q, net TIE_P6_Q TIE_P38_Q: adding pin P38.Q Tie to pin P38.Q, net TIE_P38_Q TIE_P7_Q: adding pin P7.Q Tie to pin P7.Q, net TIE_P7_Q TIE_P37_Q: adding pin P37.Q Tie to pin P37.Q, net TIE_P37_Q TIE_P8_Q: adding pin P8.Q Tie to pin P8.Q, net TIE_P8_Q TIE_P36_Q: adding pin P36.Q Tie to pin P36.Q, net TIE_P36_Q TIE_P9_Q: adding pin P9.Q Tie to pin P9.Q, net TIE_P9_Q TIE_P35_Q: adding pin P35.Q Tie to pin P35.Q, net TIE_P35_Q TIE_U4_Q: adding pin U4.Q Tie to pin U4.Q, net TIE_U4_Q TIE_U69_Q: adding pin U69.Q Tie to pin U69.Q, net TIE_U69_Q TIE_U3_Q: adding pin U3.Q Tie to pin U3.Q, net TIE_U3_Q TIE_U70_Q: adding pin U70.Q Tie to pin U70.Q, net TIE_U70_Q TIE_P10_Q: adding pin P10.Q Tie to pin P10.Q, net TIE_P10_Q TIE_P34_Q: adding pin P34.Q Tie to pin P34.Q, net TIE_P34_Q TIE_P11_Q: adding pin P11.Q Tie to pin P11.Q, net TIE_P11_Q TIE_P33_Q: adding pin P33.Q Tie to pin P33.Q, net TIE_P33_Q TIE_P13_Q: adding pin P13.Q Tie to pin P13.Q, net TIE_P13_Q TIE_P14_Q: adding pin P14.Q Tie to pin P14.Q, net TIE_P14_Q TIE_P15_Q: adding pin P15.Q Tie to pin P15.Q, net TIE_P15_Q TIE_U93_Q: adding pin U93.Q Tie to pin U93.Q, net TIE_U93_Q TIE_P16_Q: adding pin P16.Q Tie to pin P16.Q, net TIE_P16_Q TIE_P17_Q: adding pin P17.Q Tie to pin P17.Q, net TIE_P17_Q TIE_P18_Q: adding pin P18.Q Tie to pin P18.Q, net TIE_P18_Q TIE_P19_Q: adding pin P19.Q Tie to pin P19.Q, net TIE_P19_Q TIE_U88_Q: adding pin U88.Q Tie to pin U88.Q, net TIE_U88_Q TIE_U87_Q: adding pin U87.Q Tie to pin U87.Q, net TIE_U87_Q TIE_P20_Q: adding pin P20.Q Tie to pin P20.Q, net TIE_P20_Q TIE_P21_Q: adding pin P21.Q Tie to pin P21.Q, net TIE_P21_Q TIE_P23_Q: adding pin P23.Q Tie to pin P23.Q, net TIE_P23_Q TIE_P24_Q: adding pin P24.Q Tie to pin P24.Q, net TIE_P24_Q TIE_P25_Q: adding pin P25.Q Tie to pin P25.Q, net TIE_P25_Q TIE_P26_Q: adding pin P26.Q Tie to pin P26.Q, net TIE_P26_Q TIE_P27_Q: adding pin P27.Q Tie to pin P27.Q, net TIE_P27_Q TIE_U79_Q: adding pin U79.Q Tie to pin U79.Q, net TIE_U79_Q TIE_P28_Q: adding pin P28.Q Tie to pin P28.Q, net TIE_P28_Q TIE_U77_Q: adding pin U77.Q Tie to pin U77.Q, net TIE_U77_Q TIE_P29_Q: adding pin P29.Q Tie to pin P29.Q, net TIE_P29_Q TIE_P30_Q: adding pin P30.Q Tie to pin P30.Q, net TIE_P30_Q TIE_U74_Q: adding pin U74.Q Tie to pin U74.Q, net TIE_U74_Q TIE_U73_Q: adding pin U73.Q Tie to pin U73.Q, net TIE_U73_Q Tie to pullups.. TIE_PU_AM_1_O: adding pin PU.AM.1.O Tie to pin PU.AM.1.O, net TIE_PU_AM_1_O TIE_PU_BM_1_O: adding pin PU.BM.1.O Tie to pin PU.BM.1.O, net TIE_PU_BM_1_O TIE_PU_BM_2_O: adding pin PU.BM.2.O Tie to pin PU.BM.2.O, net TIE_PU_BM_2_O TIE_PU_CM_1_O: adding pin PU.CM.1.O Tie to pin PU.CM.1.O, net TIE_PU_CM_1_O TIE_PU_CM_2_O: adding pin PU.CM.2.O Tie to pin PU.CM.2.O, net TIE_PU_CM_2_O TIE_PU_DM_1_O: adding pin PU.DM.1.O Tie to pin PU.DM.1.O, net TIE_PU_DM_1_O TIE_PU_DM_2_O: adding pin PU.DM.2.O Tie to pin PU.DM.2.O, net TIE_PU_DM_2_O TIE_PU_EM_1_O: adding pin PU.EM.1.O Tie to pin PU.EM.1.O, net TIE_PU_EM_1_O TIE_PU_EM_2_O: adding pin PU.EM.2.O Tie to pin PU.EM.2.O, net TIE_PU_EM_2_O TIE_PU_FM_1_O: adding pin PU.FM.1.O Tie to pin PU.FM.1.O, net TIE_PU_FM_1_O TIE_PU_FM_2_O: adding pin PU.FM.2.O Tie to pin PU.FM.2.O, net TIE_PU_FM_2_O TIE_PU_GM_1_O: adding pimakebits: Making bitstream.. n PU.GM.1.O Tie to pin PU.GM.1.O, net TIE_PU_GM_1_O TIE_PU_GM_2_O: adding pin PU.GM.2.O Tie to pin PU.GM.2.O, net TIE_PU_GM_2_O TIE_PU_HM_1_O: adding pin PU.HM.1.O Tie to pin PU.HM.1.O, net TIE_PU_HM_1_O TIE_PU_HM_2_O: adding pin PU.HM.2.O Tie to pin PU.HM.2.O, net TIE_PU_HM_2_O TIE_PU_IM_1_O: adding pin PU.IM.1.O Tie to pin PU.IM.1.O, net TIE_PU_IM_1_O TIE_PU_IM_2_O: adding pin PU.IM.2.O Tie to pin PU.IM.2.O, net TIE_PU_IM_2_O TIE_PU_JM_1_O: adding pin PU.JM.1.O Tie to pin PU.JM.1.O, net TIE_PU_JM_1_O TIE_PU_JM_2_O: adding pin PU.JM.2.O Tie to pin PU.JM.2.O, net TIE_PU_JM_2_O TIE_PU_KM_1_O: adding pin PU.KM.1.O Tie to pin PU.KM.1.O, net TIE_PU_KM_1_O TIE_PU_KM_2_O: adding pin PU.KM.2.O Tie to pin PU.KM.2.O, net TIE_PU_KM_2_O TIE_PU_LM_1_O: adding pin PU.LM.1.O Tie to pin PU.LM.1.O, net TIE_PU_LM_1_O TIE_PU_LM_2_O: adding pin PU.LM.2.O Tie to pin PU.LM.2.O, net TIE_PU_LM_2_O TIE_PU_MM_1_O: adding pin PU.MM.1.O Tie to pin PU.MM.1.O, net TIE_PU_MM_1_O TIE_PU_AA_1_O: adding pin PU.AA.1.O Tie to pin PU.AA.1.O, net TIE_PU_AA_1_O TIE_PU_BA_1_O: adding pin PU.BA.1.O Tie to pin PU.BA.1.O, net TIE_PU_BA_1_O TIE_PU_BA_2_O: adding pin PU.BA.2.O Tie to pin PU.BA.2.O, net TIE_PU_BA_2_O TIE_PU_CA_1_O: adding pin PU.CA.1.O Tie to pin PU.CA.1.O, net TIE_PU_CA_1_O TIE_PU_CA_2_O: adding pin PU.CA.2.O Tie to pin PU.CA.2.O, net TIE_PU_CA_2_O TIE_PU_DA_1_O: adding pin PU.DA.1.O Tie to pin PU.DA.1.O, net TIE_PU_DA_1_O TIE_PU_DA_2_O: adding pin PU.DA.2.O Tie to pin PU.DA.2.O, net TIE_PU_DA_2_O TIE_PU_EA_1_O: adding pin PU.EA.1.O Tie to pin PU.EA.1.O, net TIE_PU_EA_1_O TIE_PU_EA_2_O: adding pin PU.EA.2.O Tie to pin PU.EA.2.O, net TIE_PU_EA_2_O TIE_PU_FA_1_O: adding pin PU.FA.1.O Tie to pin PU.FA.1.O, net TIE_PU_FA_1_O TIE_PU_FA_2_O: adding pin PU.FA.2.O Tie to pin PU.FA.2.O, net TIE_PU_FA_2_O TIE_PU_GA_1_O: adding pin PU.GA.1.O Tie to pin PU.GA.1.O, net TIE_PU_GA_1_O TIE_PU_GA_2_O: adding pin PU.GA.2.O Tie to pin PU.GA.2.O, net TIE_PU_GA_2_O TIE_PU_HA_1_O: adding pin PU.HA.1.O Tie to pin PU.HA.1.O, net TIE_PU_HA_1_O TIE_PU_HA_2_O: adding pin PU.HA.2.O Tie to pin PU.HA.2.O, net TIE_PU_HA_2_O TIE_PU_IA_1_O: adding pin PU.IA.1.O Tie to pin PU.IA.1.O, net TIE_PU_IA_1_O TIE_PU_IA_2_O: adding pin PU.IA.2.O Tie to pin PU.IA.2.O, net TIE_PU_IA_2_O TIE_PU_JA_1_O: adding pin PU.JA.1.O Tie to pin PU.JA.1.O, net TIE_PU_JA_1_O TIE_PU_JA_2_O: adding pin PU.JA.2.O Tie to pin PU.JA.2.O, net TIE_PU_JA_2_O TIE_PU_KA_1_O: adding pin PU.KA.1.O Tie to pin PU.KA.1.O, net TIE_PU_KA_1_O TIE_PU_KA_2_O: adding pin PU.KA.2.O Tie to pin PU.KA.2.O, net TIE_PU_KA_2_O TIE_PU_LA_1_O: adding pin PU.LA.1.O Tie to pin PU.LA.1.O, net TIE_PU_LA_1_O TIE_PU_LA_2_O: adding pin PU.LA.2.O Tie to pin PU.LA.2.O, net TIE_PU_LA_2_O TIE_PU_MA_1_O: adding pin PU.MA.1.O Tie to pin PU.MA.1.O, net TIE_PU_MA_1_O Program remaining magic boxes.. Program remaining CLB and IOB inputs.. Fix up unprogrammed IOB clocks.. Check.. Xilinx LCA MAKEBITS Ver. 5.0.0 ended normally XMAKE: 'lfsr.bit' has been made.