****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : lfsr
Version: v3.2b
Date   : Sun Apr  9 17:24:16 1995
****************************************

Operating Conditions: WCCOM   Library: xprim_3042-50
Wire Loading Model Mode: top

Design           Wire Loading Model      Library
------------------------------------------------
lfsr                   3042-50_avg       xprim_3042-50


  Startpoint: Q_reg<2> (rising edge-triggered flip-flop clocked by Clk)
  Endpoint: Q_reg<0> (rising edge-triggered flip-flop clocked by Clk)
  Path Group: Clk
  Path Type: max

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock Clk (rise edge)                    0.00       0.00
  clock network delay (ideal)              0.00       0.00
  Q_reg<2>/C (FDCE)                        0.00       0.00 r
  Q_reg<2>/Q (FDCE)                       23.92      23.92 r
  U29/O (XNOR2)                           18.97      42.89 r
  Q_reg<0>/D (FDCE)                        0.00      42.89 r
  data arrival time                                  42.89

  clock Clk (rise edge)                  100.00     100.00
  clock network delay (ideal)              0.00     100.00
  Q_reg<0>/C (FDCE)                        0.00     100.00 r
  library setup time                       0.00     100.00
  data required time                                100.00
  -----------------------------------------------------------
  data required time                                100.00
  data arrival time                                 -42.89
  -----------------------------------------------------------
  slack (MET)                                        57.11