---------------------------------------------------------------
-- L F S R . V
-- Scott Harrington
-- Spring 1995
-- VHDL source for simple GERM LFSR counter
--
-- For 3, 4, 6, 7, or 15 bit LFSR the XNOR feedback is from
-- the two most significant output bits.
-- See Xilinx Data Book p. 9-24.
----------------------------------------------------------------

-- NOTE: VLBIT TYPES ARE CONVERTED TO STD_LOGIC
-- This file gets preprocessed with cpp before it
-- becomes a .vhd file.  See Makefile.

-----------------------
-- I/O descriptions: --
-----------------------

--	Clk: FPGA TCLK
--	CE: Clock Enable to LFSR flip flops
--  CLR: Synchronous CLR to all zeros
--	Q3-0: output bits, pseudorandom sequence of length 15
--   (BUFFER type allows Q's value to be read as well as written)

ENTITY lfsr IS
	PORT (
		Clk: IN vlbit;
		CE: IN vlbit;
		CLR: IN vlbit;
		Q: BUFFER vlbit_1d(3 downto 0)
		);
END lfsr;

ARCHITECTURE behav OF lfsr IS

SIGNAL Qnext: vlbit_1d(3 downto 0);
SIGNAL feedback: vlbit;

BEGIN

	feedback <= NOT (Q(3) XOR Q(2));

	-- This is the combinational feedback logic
	LfsrComboProc: Qnext <= Q(2 downto 0) & feedback;

	-- This is the clocked process that causes flipflop to be inferred
	LfsrClockProc: PROCESS
	BEGIN
		WAIT UNTIL Clk'EVENT AND Clk='1';
		IF (CLR='1') THEN		-- infer synchronous clear
			Q <= "0000";
		ELSIF (CE='1') THEN		-- infer clock enable
			Q <= Qnext;
		END IF;
	END PROCESS;

END behav;