---------------------------------------------------------------
-- T B _ L F S R . V H D
-- Scott Harrington
-- Spring 1995
-- VHDL test bench for lfsr.v
--
-- The lfsr component implements a 4 bit cycle-15 counter with
-- synchronous enable and clear.
----------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY tb_lfsr IS
END;

ARCHITECTURE testbench OF tb_lfsr IS

SIGNAL Clk: std_logic;
SIGNAL CE: std_logic;
SIGNAL CLR: std_logic;
SIGNAL Q: std_logic_vector(3 downto 0);

COMPONENT lfsr
	PORT (
		Clk: IN std_logic;
		CE: IN std_logic;
		CLR: IN std_logic;
		Q: INOUT std_logic_vector(3 downto 0)
		);
END COMPONENT;

BEGIN

	UUT: lfsr PORT MAP (Clk, CE, CLR, Q);

	-- Set up a clk input to the unit under test
	ClockStimulusProc: PROCESS
	BEGIN
		Clk <= '1', '0' AFTER 50 ns;
		WAIT FOR 100 ns;
	END PROCESS;

	CE <= '1';

	CLRStimulusProc: PROCESS
	BEGIN
		CLR <= '1', '0' AFTER 300 ns;
		WAIT FOR 10000 ns;
	END PROCESS;

END testbench;