MPL VHDL Model Collection

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   eia. eia567ev

1.0 

  Other:  EIA-567 Component Modeling
          Specification:  Electrical View

   eia.eia567pv

1.0 

  Other:  EIA-567 Component Modeling
          Specification:  Physical View

   eia.eia567tv

1.1 

  Other:  EIA-567 Component Modeling
          Specification:  Timing View

    idt.idt_utils(body)

v1.1 

  Others:  Utility Package for IDT models

   idt.idtXXfct543

1.1 

  Other:  Octal Latched Transceiver
        w/ Latch Enable, Chip Enable, 
        and Output Enable

   idt.idtXXfct646

1.1 

  Other:  Octal Transceiver/Register
        w/ Enable and Direction Control

   idt.idtXXfct841

1.1 

  Other:  Bus interface latches
        w/ PRE, CLR, LE, and OE

   utilities.jedec_reader(body)

1.2 

  Other:  Reads jedec file and returns
        fuse map as a bit_vector.  Fuse
        
checksum also extracted and
       
verified

   utilities.mem_page_small(body)

1.2 

  Other:  Memory Model Package
        w/ Disk Paging

   utilities.memory(body)

1.2 

  Other:  Support subprograms
        for modeling memory devices

   utilities.standard_utils(body)

1.2 

  Other:  Subprograms for type
        conversions between types in
        std.standard and other support
        functions associated with package 
        std.standard

   utilities.std_logic_1164_utils(body)

1.2 

  Other:  Suprograms for type conversions
        between types in std.standard
        and ieee.std_logic_1164 and
        other support functions associated
        with package ieee.std_logic_1164

   cypress.cypress_utils(body)

1.2 

  Other:  Various support utilities

   cypress.dual_port(body)

1.1 

  Other:  Cypress Dual-Port RAM
        w/ Semaphores, Int, and Busy

   cypress.dual_port_tv(body)

1.1 

  Other:  Timing Package
        for Cypress Dual-Port RAMS

   cypress.pal20_tv(body)

1.1 

  Other:   Industry-Standard PLD,
        Timing View Package for PAL20
        Series Devices

   cypress.palc20_tv(body)

1.1 

  Other:  Reprogrammable CMOS PLD,
        Timing View Package for PALC20
        Series Devices

   cypress.ram_ce(body)

1.1 

  Other:  Cypress RAM
        w/ one CS and bussed Data Inputs
        and Data Outputs

   cypress.ram_ce_oe(body)

1.2 

  Other:  Cypress RAM
        w/ one CS, one OE, and shared I/O

   cypress.ram_ce_oe_tv(body)

1.1 

  Other:  Timing Package
        for RAM devices w/ single CE,
        single OE, and shared I/O

   cypress.ram_ce_tv(body)

1.1 

  Other:  Timing view package
        for RAM devices w/ a single CE
        and shared I/O

   ieee.std_logic_1164(body)

1.1 

  Other:  IEEE standard used to describe
          interconnection data types used
          in VHDL modeling