-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC14.VHD C:\TEMP\RTL\LOG
-- IC14.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP7.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC14
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:55:08 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC14 is
   port (
      A, B : in std_logic ;
      X, Z : out std_logic) ;
end LOGIC14 ;

architecture exemplar of LOGIC14 is
 
begin
   Z <= ( not B and  not A) or (B and A) ;
   X <= B ;

end exemplar ;