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<P><FONT SIZE=6>Processor Models</FONT></P>
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<li><DT><a href="http://www.ee.gatech.edu/users/kasyapa/vkm/html/rassp.html">RASSP Processor Modeling Effort at Georgia Institute of Technology</a><img align="bottom" src="/graphics/rassp-dev.gif">
<DD>Point of Contact: Dr. Vijay Madisetti
<DD><A HREF="http://www.ee.gatech.edu/users/kasyapa/vkm/frames/text/form.html">Form to request information on licensing GTRC models</A>
<DD>Processor Architectures
<DD>General Taxonomy Level : Behavioral, Full Functional
<DD>Created by : Georgia Institute of Technology/ Digital Signal Processing Laboratory
<P>
<li><DT><a href="http://rassp.aticorp.org/vhdl/models/processors/NEW_DLX.tar.gz">Synthesizable DLX: Generic 32-bit RISC Processor</a>
<DD>as part of a complete <a href="http://rassp.aticorp.org/vhdl/models/processors/VLSI_COURSE.tar">VLSI Design Course</a>
<DD>Description : Based on Hennessy & Patterson's generic 32-bit RISC
<DD>Processor Architecture, Synthesizable on Synopsys version 3.2a
<DD>General Taxonomy Level : RTL/Structural Version
<DD>Created by : University of Stuttgart / Department of Computer Science
<P>
<li><DT><a href="/vhdl/models/processors/dlx.tar.gz">DLX: Generic 32-bit RISC Processor</a> -- Copyright (C) 1993, Peter J. Ashenden
<DD>or <a href="/vhdl/models/processors/dlx_uncom/"><B>On-line archive</B></a>
<DD>Description : Hennessy & Patterson's generic 32-bit RISC Processor
<DD>Architecture
<DD>General Taxonomy Level : Behavioral and RTL Versions
<DD>Created by : Peter J. Ashenden (petera@cs.adelaide.edu.au)
<P>
<li><DT><a href="/vhdl/models/processors/dlx2.tar.gz">Alternate DLX: Generic 32-bit RISC Processor</a> -- a compressed tar file
<DD>Description : Hennessy & Patterson's generic 32-bit RISC Processor
<DD>Architecture
<DD>General Taxonomy Level : Behavioral Versions
<DD>Created by : Avaneendra Gupta, Paul R. Stephan
<P>
<li><a href="http://tech-www.informatik.uni-hamburg.de/vhdl/models/gl85/gl85.tar.gz">GL85: i8085 microprocessor clone</a>
(Behavioral and Structural compressed)
<DD><a href="ftp://ftp.netcom.com/pub/at/attest/bench/gl85/vhdl/behave/"> behavioral only</a> -- An On-line Archive
<DD><a href="ftp://ftp.netcom.com/pub/at/attest/bench/gl85/vhdl/rtl/">RTL only</a> -- An On-line Archive
<DD><a href="ftp://ftp.netcom.com/pub/at/attest/bench/gl85/vhdl/struct/">structural only</a> -- An On-line Archive
<DD><a href="http://tech-www.informatik.uni-hamburg.de/vhdl/models/gl85/pub/">documentation</a> -- An On-line Archive
<DD><a href="ftp://ftp.netcom.com/pub/at/attest/bench/gl85/vhdl/spt/">test vector responses</a> -- An On-line Archive
<DD></B>Description : op-code (but not pin compatible) clone of the i8085
<DD>microprocessor
<DD>General Taxonomy Level : Behavioral and structural models
<DD>Created by : Alexander Miczo (<A HREF="mailto:alex@attest.com">alex@attest.com</A>) Attest Software, Inc.
<P>
<li><DT><a href="http://www.vhdl.org/vi/vug_bbs/rbbs/I80386.VHD">i80386 Microprocessor</a> -- Copyright (C) Convergent, Inc. 1988
<DD>Description : Incomplete i80386 processor model
<DD>General Taxonomy Level : Behavioral
<DD>Created by : Mark Dakur
<P>
<li><DT><a href="http://tech-www.informatik.uni-hamburg.de/vhdl/models/m68000/m68000.vhd">M68000 microprocessor</a> and the necessary package (functions)
<DD> is contained in <a href="other.html#dde-benchmarks">the dde-benchmark suite</a>
<DD>Description : M68000 microprocessor model
<DD>General Taxonomy Level : Behavioral
<DD>Created by : Ric Heishman, Dave Hollinden, John Krautheim, Tim McBrayer
<DD>and Praveen Sinha (University of Cincinnati)
<P>
<li><DT><a href="http://tech-www.informatik.uni-hamburg.de/vhdl/models/29xx/2901.tar.gz">AMD 2901</a> -- a compressed tar file
<DD>Description : AMD 2901 4-bit microprocessor slice
<DD>General Taxonomy Level : Behavioral and Structural
<DD>Created by : Champaka Ramachandran (champaka@balboa.eng.uci.edu)
<DD>Univ. of Cal.,Irvine,
<P>
<li><DT><a href="http://tech-www.informatik.uni-hamburg.de/vhdl/models/29xx/2910.tar.gz">AMD 2910</a> -- a compressed tar file
<DD>Description : AMD 2910 bit slice
<DD>General Taxonomy Level : Dataflow and Structural
<DD>Created by : Champaka Ramachandran (champaka@balboa.eng.uci.edu)
<DD>Univ. of Cal.,Irvine,
<P>
<li><DT><a href="http://rassp.aticorp.org/vhdl/models/processors/erc32vhdl-1.0.tar.gz">ERC32 processor model</a>
<DD>Description : ERC32 is a radiation-tolerant SPARC V7 processor
<DD>developed for space applications.
<DD>General Taxonomy Level : Fully functional, timing accurate
<DD>Created by : European Space Agency
<DD><a href="http://www.estec.esa.nl/wsmwww/erc32/">Additional Information about the model</a>
<P>
<li><DT><a href="ftp://erm1.u-strasbg.fr/pub/vhdl/models.vhdl/DP32.vhdl/">DP32</a>
<DD>Description : DP32 processor model used in the VHDL cookbook
<DD>General Taxonomy Level : Behavioral
<DD>Created by :
<P>
<li><DT><a href="ftp://erm1.u-strasbg.fr/pub/vhdl/models.vhdl/Z80.vhdl/">Z80</a> -- a compressed tar file
<DD>Description : Testbench and parser for test patterns that were
<DD>generated by the Sentry test, this is not a Z80 model, but can
<DD>be used as a testbench for it.
<DD>General Taxonomy Level : Behavioral
<DD>Created by : M. Markowitz ( EDN Magazine )
<DD>W. Billowitch ( VHDL Technology Group )
<P>
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