# makefile for DLX
# 
# fnh, 12.12.94
#
#

TYPES= WORK/BV_ARITHMETIC.sim WORK/ALU_TYPES.sim WORK/DLX_TYPES.sim WORK/CACHE_TYPES.sim WORK/MEM_TYPES.sim
INSTR= WORK/DLX_INSTR.sim


WORK/BV_ARITHMETIC.sim: bv_arithmetic.vhdl
	vhdlan -c  -nc bv_arithmetic.vhdl
	vhdlan -c  -nc bv_arithmetic-body.vhdl

WORK/BV_TEST.sim:	bv_test.vhdl 
	vhdlan -c -nc bv_test.vhdl
	vhdlan -c -nc bv_test-bench.vhdl

WORK/ALU.sim:	alu_types.vhdl alu.vhdl alu-behaviour.vhdl $(TYPES) 
	vhdlan -c -nc alu.vhdl
	vhdlan -c -nc alu-behaviour.vhdl

WORK/ALU_TYPES.sim: alu_types.vhdl
	vhdlan -c -nc alu_types.vhdl

WORK/CACHE_TYPES.sim:	cache.vhdl cache_types.vhdl cache-behaviour.vhdl 
	vhdlan -c -nc cache_types.vhdl

WORK/CACHE.sim:	cache.vhdl cache_types.vhdl cache-behaviour.vhdl $(TYPES)
	vhdlan -c -nc cache.vhdl
	vhdlan -c -nc cache-behaviour.vhdl

WORK/CLOCK_GEN.sim:	clock_gen.vhdl clock_gen-behaviour.vhdl $(TYPES)
	vhdlan -c -nc clock_gen.vhdl
	vhdlan -c -nc clock_gen-behaviour.vhdl

WORK/CLOCK_GEN_TEST.sim:	clock_gen_test.vhdl clock_gen_test-bench.vhdl $(TYPES)
	vhdlan -c -nc clock_gen_test.vhdl
	vhdlan -c -nc clock_gen_test-bench.vhdl

WORK/CONTROLLER.sim:	controller.vhdl controller-behaviour.vhdl $(INSTR)
	vhdlan -c -nc controller.vhdl
	vhdlan -c -nc controller-behaviour.vhdl

WORK/DLX.sim:	dlx.vhdl $(TYPES) dlx-behaviour.vhdl dlx-instrumented.vhdl dlx-rtl.vhdl
	vhdlan -c -nc dlx.vhdl
	vhdlan -c -nc dlx-behaviour.vhdl
	vhdlan -c -nc dlx-instrumented.vhdl
	vhdlan -c -nc dlx-rtl.vhdl

WORK/DLX_TYPES.sim:	dlx_types.vhdl
	vhdlan -c -nc dlx_types.vhdl
	vhdlan -c -nc dlx_types-body.vhdl

WORK/DLX_INSTR.sim:	dlx_instr.vhdl
	vhdlan -c -nc dlx_instr.vhdl
	vhdlan -c -nc dlx_instr-body.vhdl

WORK/DLX_BUS_MONITOR.sim: dlx_bus_monitor.vhdl dlx_bus_monitor-behaviour.vhdl
	vhdlan -c -nc dlx_bus_monitor.vhdl
	vhdlan -c -nc dlx_bus_monitor-behaviour.vhdl

WORK/DLX_TEST.sim: dlx_test.vhdl dlx_test_behaviour.vhdl dlx_test-bench.vhdl dlx_test-bench_cache.vhdl WORK/DLX_BUS_MONITOR.sim WORK/DLX.sim
	vhdlan -c -nc dlx_test.vhdl
	vhdlan -c -nc dlx_test-bench.vhdl
	vhdlan -c -nc dlx_test-bench_cache.vhdl
	vhdlan -c -nc dlx_test_behaviour.vhdl



WORK/IMAGES.sim:	images.vhdl images-body.vhdl images_test.vhdl images_test-bench.vhdl
	vhdlan -c -nc images.vhdl
	vhdlan -c -nc images-body.vhdl
	vhdlan -c -nc images_test.vhdl
	vhdlan -c -nc images_test-bench.vhdl

WORK/IR.sim:	ir.vhdl ir-behaviour.vhdl
	vhdlan -c -nc ir.vhdl
	vhdlan -c -nc ir-behaviour.vhdl

WORK/LATCH.sim:	latch.vhdl latch-behaviour.vhdl
	vhdlan -c -nc latch.vhdl
	vhdlan -c -nc latch-behaviour.vhdl


WORK/MEM_TYPES.sim:	mem_types.vhdl WORK/IMAGES.sim
	vhdlan -c -nc mem_types.vhdl

WORK/MEMORY.sim:	memory.vhdl memory-behaviour.vhdl $(TYPES) WORK/CLOCK_GEN.sim
	vhdlan -c -nc memory.vhdl
	vhdlan -c -nc memory-behaviour.vhdl
	vhdlan -c -nc memory_test.vhdl
	vhdlan -c -nc memory_test-bench.vhdl

WORK/MUX2.sim: mux2.vhdl mux2-behaviour.vhdl $(TYPES)
	vhdlan -c -nc mux2.vhdl
	vhdlan -c -nc mux2-behaviour.vhdl

WORK/REG_1_OUT.sim:	reg_1_out.vhdl reg_1_out-behaviour.vhdl $(TYPES)
	vhdlan -c -nc reg_1_out.vhdl
	vhdlan -c -nc reg_1_out-behaviour.vhdl

WORK/REG_2_OUT.sim:	reg_2_out.vhdl reg_2_out-behaviour.vhdl reg_2_1_out.vhdl reg_2_1_out-behaviour.vhdl $(TYPES)
	vhdlan -c -nc reg_2_out.vhdl
	vhdlan -c -nc reg_2_out-behaviour.vhdl
	vhdlan -c -nc reg_2_1_out.vhdl
	vhdlan -c -nc reg_2_1_out-behaviour.vhdl

WORK/REG_3_OUT.sim:	reg_3_out.vhdl reg_3_out-behaviour.vhdl
	vhdlan -c -nc reg_3_out.vhdl
	vhdlan -c -nc reg_3_out-behaviour.vhdl




WORK/REG_FILE.sim:	reg_file.vhdl reg_file-behaviour.vhdl WORK/REG_1_OUT.sim WORK/REG_2_OUT.sim WORK/REG_3_OUT.sim $(TYPES)
	vhdlan -c -nc reg_file.vhdl
	vhdlan -c -nc reg_file-behaviour.vhdl










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