--
-- Rcsid[] = "$Id: regctrl0.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity regctrl0 is
port(HOUT,LOUT,WRH,WRL,
     LDLATCHBOTH,ENLATCHOUT,INCRLATCH,XTHL,LHLD,
     LOADZ,LOADW,WRWZINLATCH,ENWZOUT: out bit;
     ID0,ID1,ID2,ID3,ID4,ID8,ID10,ID11,ID12,ID13,ID14,ID15,ID16,
     ID19,M2,M3,M4,M5,T1,T2,T3,I3,LASTMT,CC: in bit);
end;

architecture structure of regctrl0 is

signal n1, n3, LHLD_SHLD, n7, n8 : bit;
signal DAD: bit;
signal n12, n16d, n17, n18, n19: bit;
signal n21, n22, n23, n25, n26, n27, n29: bit;
signal n30, n31, n33, NOP, n35, n37, n38, n39: bit;
signal n40, n44, n46: bit;
signal M2T3,M3T3,M4T2,M5T2,n71: bit;
signal LDA_STA, SHLD, LHLD_buf, XTHL_buf, LOADW_buf: bit;
signal WRWZINLATCH_buf, OUT_IN: bit;

begin
U1 : AND_gate generic map(1,1) port map(n1,LDA_STA,LHLD_SHLD);
U2 : AND_gate port map(LHLD_SHLD,LHLD_buf,SHLD);
U3 : nor_gate generic map(1,1) port map(n3,n1,M3T3);
U4 : nor_gate generic map(1,1) port map(ENLATCHOUT,LHLD_SHLD,M4,T3);

U5 : nor_gate generic map(1,1) port map(INCRLATCH,LHLD_SHLD,M4T2);
U6 : or_gate generic map(1,1) port map(OUT_IN,ID19,ID3,n7);  -- OUT/IN
U7 : and_gate generic map(1,1) port map(n7,ID10,ID11);
U8 : nor_gate generic map(1,1) port map(n8,OUT_IN,M2T3);

-- for loading and enabling the latch output to the address bus
-- for IN and OUT port instructions
--.................................................................

U10 : or_gate generic map(1,1) port map(XTHL_buf,ID19,ID12,ID3);
U10a : buf_gate port map (XTHL,XTHL_buf);
U11 : or_gate generic map(1,1) port map(DAD,ID16,ID1,n12);
U12 : inv_gate generic map(1,1) port map(n12,I3);
U15 : or_gate generic map(1,1) port map(SHLD,ID16,ID12,ID2);
U16 : or_gate generic map(1,1) port map(LHLD_buf,ID16,ID13,ID2);
U16a : buf_gate port map (LHLD,LHLD_buf);
--U16b : or_gate generic map(1,1) port map(STA,ID16,ID14,ID2);
U16c : or_gate generic map(1,1) port map(LDA_STA,ID16,n16d,ID2);
U16d : AND_gate port map (n16d,ID15,ID14);
-- Generate signals to IDENTIFY the instructions
--.................................................................
U17 : nor_gate generic map(1,1) port map(n17,LHLD_buf,M5,T3);
U18 : nor_gate generic map(1,1) port map(n18,DAD,M3T3);
U19 : nor_gate generic map(1,1) port map(n19,XTHL_buf,M5,T1);
U20 : or_gate generic map(1,1) port map(WRH,n17,n18,n19);
-- Write into H register for the above instructions in
-- different time STATES depending on the instructions
--.................................................................
U21 : nor_gate generic map(1,1) port map(n21,LHLD_buf,M4,T3);
U22 : nor_gate generic map(1,1) port map(n22,DAD,M2T3);
U23 : nor_gate generic map(1,1) port map(n23,XTHL_buf,M4,T1);
U24 : or_gate generic map(1,1) port map(WRL,n21,n22,n23);
-- Write into L register for the above instructions in
-- different time STATES depending on the instructions
--.................................................................
U25 : nor_gate generic map(1,1) port map(n25,SHLD,M5T2);
U26 : nor_gate generic map(1,1) port map(n26,DAD,M3,T2);
U27 : nor_gate generic map(1,1) port map(n27,XTHL_buf,M4T2);
U28 : or_gate generic map(1,1) port map(HOUT,n25,n26,n27);
-- Enable the outputs of H register onto 8BITBUS
--.................................................................
U29 : nor_gate generic map(1,1) port map(n29,SHLD,M4T2);
U30 : nor_gate generic map(1,1) port map(n30,DAD,M2,T2);
U31 : nor_gate generic map(1,1) port map(n31,XTHL_buf,M5T2);
U32 : or_gate generic map(1,1) port map(LOUT,n29,n30,n31);
-- Enable the outputs of L register onto 8BITBUS
--.................................................................

-- FOR LOADING THE LATCH WITH CONTENTS OF PC IN LAST m/c
-- AND LAST STATE
U33 : nor_gate generic map(1,1) port map(n33,n37,OUT_IN);
U34 : nor_gate generic map(1,1) port map(NOP,n37,ID16,ID8,ID0); -- for NOP
-- AT RESET THE INSTRUCTION REGISTER IS CLEARED TO A NOP
U35 : nor_gate generic map(1,1) port map(n35,n38,n1);
U36 : or_gate generic map(1,1) port map(LDLATCHBOTH,n33,NOP,n35,n39);
U37 : inv_gate generic map(1,1) port map(n37,LASTMT);  -- invert the last m/c and t state

--  the LHLD instruction is an exception to the above method
--  of loading the PC since the H reg. is written in M5,T3
U38 : nand_gate generic map(1,1) port map(n38,LASTMT,LHLD_buf);
U39 : nor_gate generic map(1,1) port map(n39,LHLD_buf,M5T2);
--  load PC in M5,T2

-- FOR INport and OUTport both bytes of the latch should
-- have the same contents,  so route the 8 bit internal
-- bus into both bytes of the latch
--..............................................................
U40 : NOR_gate generic map(1,1) port map(LOADZ,M2T3,n40);
U40a : AND_gate generic map(1,1) port map(n40,n1,OUT_IN,n46);
-- load the auxiliary LATCH
U41 : or_gate generic map(1,1) port map(LOADW_buf,n3,n8,n71);
U41a : buf_gate port map (LOADW,LOADW_buf);
U42 : nor_gate generic map(1,1) port map(WRWZINLATCH_buf,LHLD_SHLD,M4,T1);
U42a : buf_gate port map(WRWZINLATCH,WRWZINLATCH_buf);
U43 : or_gate generic map(1,1) port map(ENWZOUT,LOADW_buf,WRWZINLATCH_buf);
--..............................................................
U44 : and_gate generic map(1,1) port map(n44,ID2,ID4);
--U45 : OR_gate generic map(1,1) port map(n45,ID19,n44);
U46 : OR_gate generic map(1,1) port map(n46,ID19,n44,CC);

U67 : or_gate generic map(1,1) port map(M2T3,M2,T3);
U68 : or_gate generic map(1,1) port map(M3T3,M3,T3);
U69 : or_gate generic map(1,1) port map(M4T2,M4,T2);
U70 : or_gate generic map(1,1) port map(M5T2,M5,T2);

U71 : NOR_gate generic map(1,1) port map(n71,M3T3,n46);
end structure;

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