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_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 4 IR x95
-| |- Copyright (C) 1991, 1992, 1993,
|_______________| 1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
| | | | | | |
======================================================================
Compiling: s7451.vhd
Options: -d c22v10 -v1 -o2 -fo s7451.vhd
======================================================================
vhdlfe V4 IR x95: VHDL parser
Thu May 10 10:59:41 2001
Library 'work' => directory 'lc22v10'
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/opt/ecad/warp/lib/ieee/work'
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
vhdlfe: No errors.
tovif V4 IR x95: High-level synthesis
Thu May 10 10:59:42 2001
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
tovif: No errors.
topld V4 IR x95: Synthesis and optimization
Thu May 10 10:59:43 2001
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 1.
----------------------------------------------------------
Created 10 PLD nodes.
topld: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN HEADER INFORMATION (10:59:44)
Input File(s): s7451.pla
Device : C22V10
ReportFile : s7451.rpt
Program Controls:
None.
Signal Requests:
GROUP DT-OPT ALL
GROUP FAST_SLEW ALL
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
OPTIMIZATION OPTIONS (10:59:44)
Messages:
Information: Optimizing logic using best output polarity for signals:
y2 y1
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
LOGIC MINIMIZATION (10:59:45)
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
OPTIMIZATION OPTIONS (10:59:45)
Messages:
Information: Optimizing Banked Preset/Reset requirements.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN EQUATIONS (10:59:45)
/y2 =
c2 * d2
+ a2 * b2
/y1 =
c1 * d1
+ a1 * b1
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN RULE CHECK (10:59:45)
Messages:
None.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN SIGNAL PLACEMENT (10:59:45)
Messages:
Information: All signals pre-placed in user design.
C22V10
__________________________________________
not used *| 1| |24|* not used
a1 =| 2| |23|* not used
b1 =| 3| |22|= y1
c1 =| 4| |21|= y2
d1 =| 5| |20|* not used
a2 =| 6| |19|* not used
b2 =| 7| |18|* not used
c2 =| 8| |17|* not used
d2 =| 9| |16|* not used
not used *|10| |15|* not used
not used *|11| |14|* not used
not used *|12| |13|* not used
__________________________________________
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
Information: Checking for duplicate NODE logic.
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
RESOURCE ALLOCATION (10:59:45)
Information: Macrocell Utilization.
Description Used Max
______________________________________
| Dedicated Inputs | 8 | 11 |
| Clock/Inputs | 0 | 1 |
| I/O Macrocells | 2 | 10 |
______________________________________
10 / 22 = 45 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max
________________________________________
| 14 | Unused | 0 | 8 |
| 15 | Unused | 0 | 10 |
| 16 | Unused | 0 | 12 |
| 17 | Unused | 0 | 14 |
| 18 | Unused | 0 | 16 |
| 19 | Unused | 0 | 16 |
| 20 | Unused | 0 | 14 |
| 21 | y2 | 2 | 12 |
| 22 | y1 | 2 | 10 |
| 23 | Unused | 0 | 8 |
| 25 | Unused | 0 | 1 |
________________________________________
4 / 121 = 3 %
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
JEDEC ASSEMBLE (10:59:45)
Messages:
Information: Output file 's7451.jed' created.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully at 10:59:46
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