| CAUSE: | In a WYSIWYG design, the two output signals for the specified logic cell both feed I/O pins. However, to implement register packing in a WYSIWYG design, the two output signals can feed other logic cells, or one can feed an I/O pin and the other feed other logic cells, but they cannot both feed I/O pins. |
| ACTION: | Modify the design so that the two output signals do not both feed I/O pins. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |