Quartus

Port of type <clock1> of <LVDS transmitter PLL> <name> must fan out only to clk1 port of LVDS transmitter cell and to only one output pin

CAUSE: The specified clock1 port of the specified LVDS transmitter PLL feeds logic that is not a clk1 port of an LVDS transmitter and/or feeds too many output pins. The clock1 port of the LVDS transmitter PLL can feed only the clk1 port of an LVDS transmitter and no more than one output pin.
ACTION: Edit the design so the clock1 port of the LVDS transmitter PLL feeds only the clk1 port of an LVDS transmitter and no more than one output pin.

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