| CAUSE: | In a Net Declaration or Register Declaration at the specified location in a Verilog Design File (.v), you specified a vector of multibit values, such as a vector of integers like integer [0:3] int_vec. Verilog HDL does not support vectors of multibit values. |
| ACTION: | Change the multibit vector into an array. For example, you could change integer [0:3] int_vec into integer int_vec [0:3]. |
See also:
Section 3.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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