Quartus

Converted presettable and clearable register to equivalent circuits with latches. Registers will power up to an undefined state, and DEVCLRn will place the registers in an undefined state.

CAUSE: A register in a project targeted for one or more APEX 20K, APEX II, or ARM-based Excalibur, FLEX 6000 device(s) has one of the following conditions:
  • The register has both a preset and a clear signal.
  • The register has a preset signal but does not have a clear signal, and the Quartus II Compiler turned off the NOT Gate Push-Back logic option.
ACTION: No action is required. As a result, the Quartus II Compiler converted the register to equivalent circuits with latches. However, the resulting register will power up to an undefined state (X). Also, DEV_CLRn will place the register in an undefined state.

- PLDWorld -

 
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