Quartus

<+/-> <Longest or Shortest> clock path from clock <name> to <source or destination> <register or memory> is <time>

CAUSE: The Timing Analyzer is reporting the specified incremental timing information. The specified clock path represents the delay from the clock pin to the register.
ACTION: No action is required. You can view the results of timing analysis in the Compilation Report.

See also:

Running a Timing Analysis

- PLDWorld -

 
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