| CAUSE: | The Timing Analyzer is reporting that the specified type of fMAX of the specified clock is restricted to the specified performance between the specified source and destination nodes due to the Clock Low (tCL) and Clock High (tCH) I/O switching frequency limit of the target device you specified for the current design. The submessages of this message list the individual delay path times. |
| ACTION: | No action is required. If you want to increase the performance of the clock beyond these I/O switching frequency limits, specify a different device. |
See also:
Running a Timing Analysis
Specifying the Device Family & Device for Compilation
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