Quartus

<+/-> <Longest or Shortest> <register or pin> to <register or pin> delay is <time>

CAUSE: The Timing Analyzer is reporting the following specified estimated timing information:

  • For input and output registers, the delay between the specified data pin and the specified register.

  • For internal registers, the delay from the specified source register to the specified destination register.
ACTION: No action is required. You can view the results of timing analysis in the Compilation Report.

See also:

Running a Timing Analysis

- PLDWorld -

 
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