Quartus

Estimated most critical path is <register or pin> to <register or pin> delay of <time>

CAUSE: The Timing Analyzer is reporting the specified delay on the specified most critical estimated timing path in the design. These delays are calculated in the following way:

  • For input and output registers, this is the delay between the specified data pin and the specified register.

  • For internal registers, this is the delay from the specified source register to the specified destination register.
ACTION: No action is required. View the timing analysis results in the Report window and list and locate the timing paths to identify and correct the paths that do not meet the requirements.

See also:

Running a Timing Analysis

- PLDWorld -

 
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