Quartus

Found hold time violation between source pin or register <name> and destination pin or register <name> for clock <name> (Hold time is <time>)


CAUSE: The Timing Analyzer is reporting that it found a tH violation between the specified source pin or register and the specified destination pin or register for the specified clock. This violation occurs when the data path delay plus the specified source register's clock-to-out delay is less than the clock skew delay plus the destination register's hold time.
ACTION: No action is required. You can click the + icon to expand this message in the Messages window and display the intermediate time increments used to calculate the tH. You can view the results of timing analysis in the Compilation Report. You can try several methods to correct this violation. You can add delays between the source and destination registers by adding hard LCELL primitives between the two registers. You can also correct positive hold times by using global clock pins to clock both registers. If the source is a pin and you have turned on Include external delays to and from device pins in fmax calculations, you can correct the positive hold time by adding or increasing default external delays, or by adding or increasing external delays individually.

See also:

Running a Timing Analysis

- PLDWorld -

 

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