Quartus

<+/-> Register <name> has a <high or low> minimum pulse width requirement of <time>


CAUSE: The Timing Analyzer is reporting the specified actual minimum pulse width requirement of the specified register, as determined by either the clock low (tCL) or clock high (tCH) limits inherent in the current target device.
ACTION: No action is required.

See also:

Overview: Using the Timing Analyzer
Running a Timing Analysis

- PLDWorld -

 

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