In the current design, the Design Assistant found the specified number of structures where a clock drives the design's registers in one of the following ways:

• The clock drives registers that have clock inputs that trigger on the positive edge of the clock, and other registers that have clock inputs that trigger on the negative edge of the clock.

• The clock drives only registers that have clock inputs that all trigger on either the positive or negative edge of the clock, but the design inverts the clock before driving some of the registers.

These structures can cause various design problems, including an increase in timing requirement complexity and difficulties when optimizing a design for a HardCopy device. Also, because registers are not clocked on the same edge in the design, synchronous resetting is impossible. When a design inverts the clock, additional design problems may occur; for example, the inverted clock may be mapped to regular logic or may not contain the correct time relationship to the original clock.

The registers that synchronize gated clocks and resets are sometimes triggered by different clock edges. However, these registers do not cause problems in the design.

The submessage(s) of this message list the structure(s) that the Design Assistant found.