You turned on the Fast I/O logic option for the specified node so that the node can be implemented in a fast input register. However, the specified node does not qualify to be a fast input register for one of the following reasons:

• The node is not register or the node is not input pin.

• The register node is not implemented as a D flipflop.

• The data input to the register is not directly fed by a single input pin; i.e., there may be logic between the pin and the register.

• The register node feeds an output pin.

• The register is assigned to a buried logic cell.

• The register is fed by a BIDIR pin.

• Inconsistent location assignment between the input pin and the register.

• Conflicting fast input register option on both nodes.

• The input pin is feeding the register through an inversion. This might be a result of a not-gate-push-back being performed on the register if the inversion is originally not there.

Perform one of the following actions:

• Make sure the node is a register or is an input pin to the datain register.

• Implement the register as a D flipflop.

• Change the logic so that only a single input pin feeds the data input to the register.

• Change the logic so that the register does not feed an output pin.

• Make sure the register is not assigned to a buried logic cell.

• Make sure the register is not fed by a BIDIR pin.

• Make sure the location assignment between both nodes is consistent.

• Remove the fast input register option in either one of the node.

• Turn off NOT Gate Push-Back for the register.