| CAUSE: | In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified a set of registers that act as a RAM, and specified that data is written to the RAM on the positive edge of the RAM's write clock. When the Compiler created the specified node as a RAM using the registers, it converted the registers into a RAM megafunction to implement the register logic with an Embedded System Block (ESB) on the target device you specified for the current design. However, data is written to the ESB on the negative edge of the ESB's write clock. Because the original design specified that data is written to the RAM on the positive edge of the RAM's write clock, the functionality of the ESB is not identical to the functionality of the RAM in the original design. |
| ACTION: | If you intended the Compiler to convert the registers into a RAM megafunction to implement the register logic with an ESB, and you do not mind if the functionality of the ESB is not identical to the functionality of the RAM in the original design, no action is required. If you want the Compiler to use a RAM megafunction, but you want to avoid receiving this message in the future, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of a RAM megafunction. If you want the functionality of the RAM in the original design to be the same as functionality that is implemented in the target device, prevent the Compiler from converting the registers into a RAM megafunction by turning off the Auto RAM Replacement logic option. |
See also:
Assigning Options for Entities Only
Overview: Making Assignments
Specifying the Device Family & Device for Compilation
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