Quartus

Both read enable clear and read address clear asserted during read cycle at time <time> on read logic register of Embedded System Block memory segment <name>

CAUSE: Both read enable clear and read address clear were asserted during a read cycle at the specified time on the read logic register of the specified Embedded System Block (ESB) memory segment. Read enable clear and read address clear cannot be asserted at the same time during a read cycle.
ACTION: Edit the vector source file so read enable clear and read address clear are not both asserted during a read cycle.

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