This directory contains files for simulating a Sigma-Delta
   converter using anaVHDL.

   To simulate (using the MCC VHDL simulator):

   1. Create a directory by name "work" in your current directory
      (directory where the source files are stored).
   2. Copy the files "opamp" to "INPUT.TEXTIO1" and "lowpass" to 
      "INPUT.TEXTIO2".
   3. Copy the Makefile into your directory and change the path of 
      source, sim, work and the output files in the first three lines 
      of the Makefile corresponding to your path.
   4. Use the Makefile to analyze and simulate the circuit.