-------- SIMTEL20 VHDL Repository Prologue ------------
--
-- Unit name    : DoD/Intermetrics 1076 VDHL Shared Test Suite Known Bugs
-- Version      : See individual files contained herein. %W% %G%
-- Author       : Steve Grout as Editor
--              : MCC 
--              : 3500 West Balcones Center Dr.
--              : Austin, TX 78759
-- DDN Address  : grout@mcc.com
-- Copyright    : See individual files contained herein.
-- Date created : See individual files contained herein.
-- Release date : July 1988
-- Last update  : August 1988
-- Machine/System Analyzed/Simulated on:  Not analyzed or simulated
--              : VHDL Version - 1076-1987 IEEE Std.
--
---------------------------------------------------------------
--
-- Keywords     : test, analyzer, syntax, semantics, 1076, Intermetrics, DoD
--
-- Abstract     :
--                This file describes a set of problems known to exist
--                in the test suite for version 1076-1987 IEEE Std VHDL
--                language.  These problems were reported to this writer
--                by those indicated below.  As soon as the below problems
--                have been corrected, fixes for the tests will be distributed
--                as UNIX 'diff' files.
--
--                We solicit comments, bugs, and corrections on these
--                tests and will post updates back to this same
--                distribution as soon as we get them.
--
------------------ Revision history ---------------------------
--
-- DATE         VERSION    AUTHOR                  HISTORY
-- August 1988    1.0   Editor: Steve Grout        Original
--
------------------ Distribution and Copyright -----------------
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-- This description is copyright by the author.
--
-- This description is released to the VHDL community.
-- This description is released to the Public Domain (note:
--   Hardware descriptions released to the Public Domain are not subject
--   to copyright protection).
-- Restrictions on use or distribution:  NONE
--
------------------ Disclaimer ---------------------------------
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--
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-------------------END-PROLOGUE--------------------------------

BUG REPORT: The following are inputs from CAD Language Systems Inc.
(CLSI) after reviewing the shared test suite posted on or about July
1988.

Paul Menchini, Director of Research and Development at CLSI,
reports in part the following items noted in the subject shared
VHDL test suite:

    1. RETURN statements are not allowed in 1076 processes as they were
   previously in 7.2.  In 1076, RETURN statements are only allowed in 
   subprogram bodies.

    2. The syntax of ATTRIBUTE declarations and specifications has 
   changed from 7.2 to 1076.

    3. The syntax of COMPONENT declarations has changed from 7.2 to 1076:
   They now must end with the keywords 'END COMPONENTS'.

    4. The PORT and GENERIC maps of COMPONENT instantiations in 1076 are
   introduced respectively with the keywords 'PORT MAP' and 'GENERIC MAP'.
   Note that in 7.2 only the keywords PORT and GENERIC respectively were
   used. (Also note that the order of the map clauses has been reversed
   in 1076 with respect to 7.2.)

    5. We seem to have interpreted the visibility rules differently from
   the way you did.  We understand the USE clause "USE P.ALL" to be illegal
   unless it is proceeded by "USE WORK.P ;" as P is not directly visible by
   default.  We typically use USE clauses of the form, "USE WORK.P.ALL ;" to
   establish visibility of the declarations of P in another unit.

    6. One late change made to 1076 was that GENERATE statements are now
   required to have a label.  Note that this label was optional in 1076/B
   (IEEE VHDL draft definition), but was added at the last moment as part
   of the work in straightening out indexed labels.

    7. The syntax of COMPONENT specifications has changed between 7.2 and
   1076.
   ======================================================================

Editor's Note:  We agree with each the above items and are right now in
the process of making the above corrections to the test suite. 

We are VERY greatful to both CLSI and Paul Menchini for identifying
these problems with the tests.  It will be only in that spirit that we
will indeed be able to pull together an industry shared VHDL test suite
as we all try to work towards formal VHDL validation.  --jsgrout