--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.cpu_core.interface
--
-- Author : Michael Mayer (mrmayer@computer.org),
-- Dr. Hardy J. Pottinger,
-- Department of Electrical Engineering
-- University of Missouri - Rolla
--
-- Created at : 09/22/98 19:32:52
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;
ENTITY cpu_core IS
PORT(
ac : IN std_logic ;
acc : IN std_logic_vector( 7 DOWNTO 0 ) ;
acknow : IN std_logic ;
cy : IN std_logic ;
int_clk : IN std_logic ;
int_rst : IN std_logic ;
ir : IN std_logic_vector( 7 DOWNTO 0 ) ;
new_ir : IN std_logic ;
ov : IN std_logic ;
rs : IN std_logic_vector( 1 DOWNTO 0 ) ;
ac_out : OUT std_logic ;
addr_gb : OUT std_logic_vector( 7 DOWNTO 0 ) ;
cmp_true : OUT std_logic ;
cy_out : OUT std_logic ;
dec_rd_sp : OUT std_logic ;
inc_wr_sp : OUT std_logic ;
indirect_sel : OUT std_logic ;
ov_out : OUT std_logic ;
rd_gb : OUT std_logic ;
rd_pmem1 : OUT std_logic ;
rd_pmem2 : OUT std_logic ;
read_latch : OUT std_logic ;
wr_acc : OUT std_logic ;
wr_gb : OUT std_logic ;
wr_out : OUT std_logic ;
data_gb : INOUT std_logic_vector( 7 DOWNTO 0 )
);
-- Declarations
END cpu_core ;
--
-- VHDL Architecture mc8051.cpu_core.struct
--
-- Created:
-- by - mrmayer.UNKNOWN (eceultra6.ece.umr.edu)
-- at - 19:32:58 09/22/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.cpu_pack.all;
USE mc8051.synth_pack.all;
LIBRARY mc8051;
ARCHITECTURE struct OF cpu_core IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL alu_cmd : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL alu_result : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL alu_second_result : std_logic;
SIGNAL bit_loc : std_logic_vector( 2 DOWNTO 0 ) ;
SIGNAL cpu_done : std_logic;
SIGNAL cpu_rst : std_logic;
SIGNAL data_alu : std_logic_vector( 2 DOWNTO 0 ) ;
SIGNAL data_dest : std_logic_vector( 2 DOWNTO 0 ) ;
SIGNAL data_t1 : std_logic_vector( 2 DOWNTO 0 ) ;
SIGNAL data_t2 : std_logic_vector( 2 DOWNTO 0 ) ;
SIGNAL dest_cmd : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL set_ac_ov : std_logic;
SIGNAL set_cy : std_logic;
SIGNAL t1_cmd : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL t2_cmd : std_logic_vector( 3 DOWNTO 0 ) ;
SIGNAL tmp1 : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL tmp1_done : std_logic;
SIGNAL tmp2 : std_logic_vector( 7 DOWNTO 0 ) ;
SIGNAL two_dests : std_logic;
SIGNAL use_acc_0 : std_logic;
SIGNAL use_cy : std_logic;
-- Component Declarations
COMPONENT al_unit
PORT (
ac : IN std_logic;
alu_cmd : IN std_logic_vector( 3 DOWNTO 0 );
bit_loc : IN std_logic_vector( 2 DOWNTO 0 );
cpu_rst : IN std_logic;
cy : IN std_logic;
data_alu : IN std_logic_vector( 2 DOWNTO 0 );
int_clk : IN std_logic;
ov : IN std_logic;
set_ac_ov : IN std_logic;
set_cy : IN std_logic;
tmp1 : IN std_logic_vector( 7 DOWNTO 0 );
tmp1_done : IN std_logic;
tmp2 : IN std_logic_vector( 7 DOWNTO 0 );
use_acc_0 : IN std_logic;
use_cy : IN std_logic;
ac_out : OUT std_logic;
alu_result : OUT std_logic_vector( 7 DOWNTO 0 );
cmp_true : OUT std_logic;
cy_out : OUT std_logic;
ov_out : OUT std_logic
);
END COMPONENT;
COMPONENT ir_decoder
PORT (
alu_second_result : IN std_logic;
cpu_rst : IN std_logic;
cy : IN std_logic;
int_clk : IN std_logic;
ir : IN std_logic_vector( 7 DOWNTO 0 );
new_ir : IN std_logic;
alu_cmd : OUT std_logic_vector( 3 DOWNTO 0 );
data_alu : OUT std_logic_vector( 2 DOWNTO 0 );
data_dest : OUT std_logic_vector( 2 DOWNTO 0 );
data_t1 : OUT std_logic_vector( 2 DOWNTO 0 );
data_t2 : OUT std_logic_vector( 2 DOWNTO 0 );
dest_cmd : OUT std_logic_vector( 3 DOWNTO 0 );
read_latch : OUT std_logic;
set_ac_ov : OUT std_logic;
set_cy : OUT std_logic;
t1_cmd : OUT std_logic_vector( 3 DOWNTO 0 );
t2_cmd : OUT std_logic_vector( 3 DOWNTO 0 );
two_dests : OUT std_logic;
use_acc_0 : OUT std_logic;
use_cy : OUT std_logic
);
END COMPONENT;
COMPONENT tmp_regs
PORT (
acc : IN std_logic_vector( 7 DOWNTO 0 );
acknow : IN std_logic;
alu_result : IN std_logic_vector( 7 DOWNTO 0 );
cpu_rst : IN std_logic;
data_dest : IN std_logic_vector( 2 DOWNTO 0 );
data_t1 : IN std_logic_vector( 2 DOWNTO 0 );
data_t2 : IN std_logic_vector( 2 DOWNTO 0 );
dest_cmd : IN std_logic_vector( 3 DOWNTO 0 );
int_clk : IN std_logic;
new_ir : IN std_logic;
rs : IN std_logic_vector( 1 DOWNTO 0 );
t1_cmd : IN std_logic_vector( 3 DOWNTO 0 );
t2_cmd : IN std_logic_vector( 3 DOWNTO 0 );
two_dests : IN std_logic;
addr_gb : OUT std_logic_vector( 7 DOWNTO 0 );
alu_second_result : OUT std_logic;
bit_loc : OUT std_logic_vector( 2 DOWNTO 0 );
cpu_done : OUT std_logic;
dec_rd_sp : OUT std_logic;
inc_wr_sp : OUT std_logic;
indirect_sel : OUT std_logic;
rd_gb : OUT std_logic;
rd_pmem1 : OUT std_logic;
rd_pmem2 : OUT std_logic;
tmp1 : OUT std_logic_vector( 7 DOWNTO 0 );
tmp1_done : OUT std_logic;
tmp2 : OUT std_logic_vector( 7 DOWNTO 0 );
wr_acc : OUT std_logic;
wr_gb : OUT std_logic;
wr_out : OUT std_logic;
data_gb : INOUT std_logic_vector( 7 DOWNTO 0 )
);
END COMPONENT;
-- Optional embedded configurations
--synopsys translate_off
FOR ALL : al_unit USE ENTITY mc8051.al_unit;
FOR ALL : ir_decoder USE ENTITY mc8051.ir_decoder;
FOR ALL : tmp_regs USE ENTITY mc8051.tmp_regs;
--synopsys translate_on
BEGIN
-- Architecture concurrent statements
-- HDL Text Block 1
cpu_rst <= int_rst OR cpu_done;
-- Instance port mappings.
I3 : al_unit
PORT MAP (
ac => ac,
alu_cmd => alu_cmd(3 downto 0),
bit_loc => bit_loc(2 downto 0),
cpu_rst => cpu_rst,
cy => cy,
data_alu => data_alu(2 downto 0),
int_clk => int_clk,
ov => ov,
set_ac_ov => set_ac_ov,
set_cy => set_cy,
tmp1 => tmp1(7 downto 0),
tmp1_done => tmp1_done,
tmp2 => tmp2(7 downto 0),
use_acc_0 => use_acc_0,
use_cy => use_cy,
ac_out => ac_out,
alu_result => alu_result(7 downto 0),
cmp_true => cmp_true,
cy_out => cy_out,
ov_out => ov_out
);
I2 : ir_decoder
PORT MAP (
alu_second_result => alu_second_result,
cpu_rst => cpu_rst,
cy => cy,
int_clk => int_clk,
ir => ir(7 downto 0),
new_ir => new_ir,
alu_cmd => alu_cmd(3 downto 0),
data_alu => data_alu(2 downto 0),
data_dest => data_dest(2 downto 0),
data_t1 => data_t1(2 downto 0),
data_t2 => data_t2(2 downto 0),
dest_cmd => dest_cmd(3 downto 0),
read_latch => read_latch,
set_ac_ov => set_ac_ov,
set_cy => set_cy,
t1_cmd => t1_cmd(3 downto 0),
t2_cmd => t2_cmd(3 downto 0),
two_dests => two_dests,
use_acc_0 => use_acc_0,
use_cy => use_cy
);
I0 : tmp_regs
PORT MAP (
acc => acc(7 downto 0),
acknow => acknow,
alu_result => alu_result(7 downto 0),
cpu_rst => cpu_rst,
data_dest => data_dest(2 downto 0),
data_t1 => data_t1(2 downto 0),
data_t2 => data_t2(2 downto 0),
dest_cmd => dest_cmd(3 downto 0),
int_clk => int_clk,
new_ir => new_ir,
rs => rs(1 downto 0),
t1_cmd => t1_cmd(3 downto 0),
t2_cmd => t2_cmd(3 downto 0),
two_dests => two_dests,
addr_gb => addr_gb(7 downto 0),
alu_second_result => alu_second_result,
bit_loc => bit_loc(2 downto 0),
cpu_done => cpu_done,
dec_rd_sp => dec_rd_sp,
inc_wr_sp => inc_wr_sp,
indirect_sel => indirect_sel,
rd_gb => rd_gb,
rd_pmem1 => rd_pmem1,
rd_pmem2 => rd_pmem2,
tmp1 => tmp1(7 downto 0),
tmp1_done => tmp1_done,
tmp2 => tmp2(7 downto 0),
wr_acc => wr_acc,
wr_gb => wr_gb,
wr_out => wr_out,
data_gb => data_gb(7 downto 0)
);
END struct;
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