Copyright 1994-1997, Concept Engineering GmbH. All Rights Reserved.
netscope
-symlib /usr/local/exemplar/lib/sym/xi.eds
-critical_path {}
/home/classes/ws97/mrmayer/8051ren/src/al_unit_spec.tim
-show_top_cell
EDIF parser 6.4: reading `/home/classes/ws97/mrmayer/8051ren/src/al_unit_spec.tim'
flags=(+pre_ref -verbose(..) +merge_commentGr +merge_figure)
ERR: bad string - line 51
ERR: bad string - line 67
ERR: bad string - line 83
ERR: bad string - line 113
ERR: bad string - line 150
ERR: bad string - line 174
ERR: bad string - line 190
Completing 0+384 Instance (viewRef (cellRef...))
Completing 0+0 PortImpl (portRef ...)
Completing 0+0 PortInstance (portRef ...)
Completing 0+0 Figure (figureGrpRef ...)
Completing 0+0 Display (figureGrpRef ...)
Completing 0+1 Design (cellRef...)
Completing 0+0 PropertyDis. (propertyRef...)
Completing 0+436 Nets (portRef...)
... 1655 new PortInstance have beed created
Completing 0+0 Interfaces (portRef...)
EDIF parser 6.4: scanning index file `/usr/local/exemplar/lib/sym/xi.idx'
EDIF parser 6.4: reading 11 cells from `/usr/local/exemplar/lib/sym/xi.eds'
flags=(+pre_ref -verbose(..) -merge_commentGr -merge_figure)
Completing 0+0 Instance (viewRef (cellRef...))
Completing 0+37 PortImpl (portRef ...)
Completing 0+0 PortInstance (portRef ...)
Completing 0+95 Figure (figureGrpRef ...)
Completing 0+48 Display (figureGrpRef ...)
Completing 0+0 Design (cellRef...)
Completing 0+0 PropertyDis. (propertyRef...)
Completing 0+0 Nets (portRef...)
Completing 0+0 Interfaces (portRef...)
al_unit: new NetBundle bit_loc + Net bit_loc(2)
al_unit: NetBundle bit_loc + Net bit_loc(1)
al_unit: NetBundle bit_loc + Net bit_loc(0)
al_unit: new NetBundle tmp1 + Net tmp1(7)
al_unit: NetBundle tmp1 + Net tmp1(6)
al_unit: NetBundle tmp1 + Net tmp1(5)
al_unit: NetBundle tmp1 + Net tmp1(4)
al_unit: NetBundle tmp1 + Net tmp1(3)
al_unit: NetBundle tmp1 + Net tmp1(2)
al_unit: NetBundle tmp1 + Net tmp1(1)
al_unit: NetBundle tmp1 + Net tmp1(0)
al_unit: new NetBundle tmp2 + Net tmp2(7)
al_unit: NetBundle tmp2 + Net tmp2(6)
al_unit: NetBundle tmp2 + Net tmp2(5)
al_unit: NetBundle tmp2 + Net tmp2(4)
al_unit: NetBundle tmp2 + Net tmp2(3)
al_unit: NetBundle tmp2 + Net tmp2(2)
al_unit: NetBundle tmp2 + Net tmp2(1)
al_unit: NetBundle tmp2 + Net tmp2(0)
al_unit: new NetBundle alu_cmd + Net alu_cmd(2)
al_unit: NetBundle alu_cmd + Net alu_cmd(3)
al_unit: NetBundle alu_cmd + Net alu_cmd(1)
al_unit: NetBundle alu_cmd + Net alu_cmd(0)
al_unit: new NetBundle data_alu + Net data_alu(0)
al_unit: NetBundle data_alu + Net data_alu(2)
al_unit: NetBundle data_alu + Net data_alu(1)
al_unit: new NetBundle alu_result + Net alu_result(0)
al_unit: NetBundle alu_result + Net alu_result(1)
al_unit: NetBundle alu_result + Net alu_result(2)
al_unit: NetBundle alu_result + Net alu_result(3)
al_unit: NetBundle alu_result + Net alu_result(4)
al_unit: NetBundle alu_result + Net alu_result(5)
al_unit: NetBundle alu_result + Net alu_result(6)
al_unit: NetBundle alu_result + Net alu_result(7)
Creating Symbol for Cell _InConn.
Creating Symbol for Cell _OutConn.
Creating Symbol for Cell _InOutConn.
Creating Symbol for Cell _PageInConn.
Creating Symbol for Cell _PageOutConn.
Creating Symbol for Cell al_unit.spec
Creating Symbol for Cell CY4.NETLIST
Creating Symbol for Cell CY4_39.NETLIST
Creating Symbol for Cell CY4_18.NETLIST
Creating Symbol for Cell CY4_42.NETLIST
Creating Symbol for Cell CY4_25.NETLIST
Creating Symbol for Cell CY4_02.NETLIST
Creating Symbol for Cell CY4_01.NETLIST
Creating Symbol for Cell F4_LUT.NETLIST
Creating Symbol for Cell F2_LUT.NETLIST
Creating Symbol for Cell H2_LUT.NETLIST
Creating Symbol for Cell F3_LUT.NETLIST
Creating Symbol for Cell H3_LUT.NETLIST
Schematic Generator 5.3 (97/05/21)
Started Thu Sep 3 00:40:08 1998
Created 29 Symbols, 405 Comps, 394 Nets 1662 Pins 0.0s 147K
Split page 1 0.0s 147K
Level Assignment 0.0s 150K
Process Nets 0.0s 150K
Component Placement 0.0s 151K
Total Placement Component-Iterations = 26 0.0s 151K
Adjust Y Spacing 0.0s 151K
Channel Routing 0.0s 152K
Adjust X Spacing 0.0s 153K
Building Wires 0.0s 153K
Split page 2 0.0s 155K
Level Assignment 0.1s 158K
Process Nets 0.1s 158K
Component Placement 0.1s 162K
Total Placement Component-Iterations = 509 0.1s 162K
Adjust Y Spacing 0.1s 162K
Channel Routing 0.1s 162K
Adjust X Spacing 0.1s 163K
Building Wires 0.1s 163K
Split page 3 0.1s 165K
Level Assignment 0.1s 168K
Process Nets 0.1s 168K
Component Placement 0.1s 168K
Total Placement Component-Iterations = 75 0.1s 168K
Adjust Y Spacing 0.1s 169K
Channel Routing 0.1s 169K
Adjust X Spacing 0.1s 169K
Building Wires 0.1s 169K
Split page 4 0.1s 170K
Level Assignment 0.1s 174K
Process Nets 0.1s 174K
Component Placement 0.1s 180K
Total Placement Component-Iterations = 767 0.1s 181K
Adjust Y Spacing 0.1s 181K
Channel Routing 0.1s 181K
Adjust X Spacing 0.2s 182K
Building Wires 0.2s 182K
Split page 5 0.2s 186K
Level Assignment 0.2s 189K
Process Nets 0.2s 189K
Component Placement 0.2s 189K
Total Placement Component-Iterations = 70 0.2s 189K
Adjust Y Spacing 0.2s 189K
Channel Routing 0.2s 189K
Adjust X Spacing 0.2s 189K
Building Wires 0.2s 189K
Split page 6 0.2s 190K
Level Assignment 0.2s 193K
Process Nets 0.2s 193K
Component Placement 0.2s 193K
Total Placement Component-Iterations = 103 0.2s 193K
Adjust Y Spacing 0.2s 193K
Channel Routing 0.2s 194K
Adjust X Spacing 0.2s 194K
Building Wires 0.2s 194K
Split page 7 0.2s 194K
Level Assignment 0.2s 197K
Process Nets 0.2s 197K
Component Placement 0.2s 198K
Total Placement Component-Iterations = 79 0.2s 198K
Adjust Y Spacing 0.2s 198K
Channel Routing 0.2s 198K
Adjust X Spacing 0.2s 198K
Building Wires 0.2s 198K
Split page 8 0.2s 199K
Level Assignment 0.2s 203K
Process Nets 0.2s 203K
Component Placement 0.2s 204K
Total Placement Component-Iterations = 79 0.2s 204K
Adjust Y Spacing 0.2s 204K
Channel Routing 0.2s 204K
Adjust X Spacing 0.2s 204K
Building Wires 0.2s 204K
Split page 9 0.2s 205K
Level Assignment 0.2s 209K
Process Nets 0.2s 209K
Component Placement 0.2s 211K
Total Placement Component-Iterations = 331 0.2s 211K
Adjust Y Spacing 0.2s 212K
Channel Routing 0.2s 212K
Adjust X Spacing 0.2s 212K
Building Wires 0.2s 212K
Split page 10 0.2s 214K
Level Assignment 0.3s 217K
Process Nets 0.3s 217K
Component Placement 0.3s 219K
Total Placement Component-Iterations = 90 0.3s 220K
Adjust Y Spacing 0.3s 220K
Channel Routing 0.3s 220K
Adjust X Spacing 0.3s 220K
Building Wires 0.3s 220K
Split page 11 0.3s 222K
Level Assignment 0.3s 227K
Process Nets 0.3s 227K
Component Placement 0.3s 231K
Total Placement Component-Iterations = 452 0.3s 232K
Adjust Y Spacing 0.3s 232K
WAR: Sheet size overflow: Try heightLimit=9.15
Channel Routing 0.3s 232K
Adjust X Spacing 0.3s 232K
Building Wires 0.3s 232K
Split page 12 0.3s 236K
Level Assignment 0.3s 240K
Process Nets 0.3s 240K
Component Placement 0.3s 242K
Total Placement Component-Iterations = 54 0.3s 242K
Adjust Y Spacing 0.3s 242K
Channel Routing 0.4s 242K
Adjust X Spacing 0.4s 242K
Building Wires 0.4s 242K
Split page 13 0.4s 244K
Level Assignment 0.4s 250K
Process Nets 0.4s 250K
Component Placement 0.4s 252K
Total Placement Component-Iterations = 651 0.4s 252K
Adjust Y Spacing 0.4s 252K
Channel Routing 0.4s 252K
Adjust X Spacing 0.4s 252K
Building Wires 0.4s 252K
Split page 14 0.4s 255K
Level Assignment 0.4s 260K
Process Nets 0.4s 260K
Component Placement 0.4s 261K
Total Placement Component-Iterations = 262 0.4s 262K
Adjust Y Spacing 0.4s 262K
Channel Routing 0.4s 262K
Adjust X Spacing 0.4s 262K
Building Wires 0.4s 262K
Split page 15 0.4s 265K
Level Assignment 0.4s 270K
Process Nets 0.4s 270K
Component Placement 0.4s 275K
Total Placement Component-Iterations = 834 0.5s 275K
Adjust Y Spacing 0.5s 275K
Channel Routing 0.5s 276K
Adjust X Spacing 0.5s 276K
Building Wires 0.5s 276K
Split page 16 0.5s 280K
Level Assignment 0.5s 283K
Process Nets 0.5s 283K
Component Placement 0.5s 283K
Total Placement Component-Iterations = 145 0.5s 283K
Adjust Y Spacing 0.5s 284K
Channel Routing 0.5s 284K
Adjust X Spacing 0.5s 284K
Building Wires 0.5s 284K
Split page 17 0.5s 285K
Level Assignment 0.5s 289K
Process Nets 0.5s 289K
Component Placement 0.5s 290K
Total Placement Component-Iterations = 326 0.5s 291K
Adjust Y Spacing 0.5s 291K
Channel Routing 0.5s 291K
Adjust X Spacing 0.5s 291K
Building Wires 0.5s 291K
Split page 18 0.5s 293K
Level Assignment 0.6s 296K
Process Nets 0.6s 296K
Component Placement 0.6s 297K
Total Placement Component-Iterations = 161 0.6s 297K
Adjust Y Spacing 0.6s 297K
Channel Routing 0.6s 297K
Adjust X Spacing 0.6s 297K
Building Wires 0.6s 297K
Split page 19 0.6s 299K
Level Assignment 0.6s 303K
Process Nets 0.6s 303K
Component Placement 0.6s 303K
Total Placement Component-Iterations = 240 0.6s 304K
Adjust Y Spacing 0.6s 304K
Channel Routing 0.6s 304K
Adjust X Spacing 0.6s 304K
Building Wires 0.6s 304K
Split page 20 0.6s 306K
Level Assignment 0.6s 310K
Process Nets 0.6s 310K
Component Placement 0.6s 310K
Total Placement Component-Iterations = 267 0.6s 311K
Adjust Y Spacing 0.6s 311K
Channel Routing 0.6s 311K
Adjust X Spacing 0.6s 311K
Building Wires 0.6s 311K
Split page 21 0.6s 313K
Level Assignment 0.6s 316K
Process Nets 0.6s 316K
Component Placement 0.6s 316K
Total Placement Component-Iterations = 208 0.6s 317K
Adjust Y Spacing 0.6s 317K
Channel Routing 0.6s 317K
Adjust X Spacing 0.6s 317K
Building Wires 0.6s 317K
Split page 22 0.6s 319K
Level Assignment 0.6s 322K
Process Nets 0.6s 322K
Component Placement 0.6s 322K
Total Placement Component-Iterations = 168 0.6s 322K
Adjust Y Spacing 0.6s 322K
Channel Routing 0.6s 322K
Adjust X Spacing 0.6s 322K
Building Wires 0.6s 322K
Split page 23 0.6s 324K
Level Assignment 0.7s 328K
Process Nets 0.7s 328K
Component Placement 0.7s 329K
Total Placement Component-Iterations = 172 0.7s 329K
Adjust Y Spacing 0.7s 329K
Channel Routing 0.7s 329K
Adjust X Spacing 0.7s 329K
Building Wires 0.7s 329K
Split page 24 0.7s 331K
Level Assignment 0.7s 333K
Process Nets 0.7s 333K
Component Placement 0.7s 334K
Total Placement Component-Iterations = 223 0.7s 334K
Adjust Y Spacing 0.7s 334K
Channel Routing 0.7s 334K
Adjust X Spacing 0.7s 335K
Building Wires 0.7s 335K
Split page 25 0.7s 336K
Level Assignment 0.7s 339K
Process Nets 0.7s 339K
Component Placement 0.7s 339K
Total Placement Component-Iterations = 210 0.7s 340K
Adjust Y Spacing 0.7s 340K
Channel Routing 0.7s 340K
Adjust X Spacing 0.7s 340K
Building Wires 0.7s 340K
Split page 26 0.7s 342K
Level Assignment 0.7s 344K
Process Nets 0.7s 344K
Component Placement 0.7s 344K
Total Placement Component-Iterations = 102 0.7s 344K
Adjust Y Spacing 0.7s 344K
Channel Routing 0.7s 344K
Adjust X Spacing 0.7s 344K
Building Wires 0.7s 344K
Split page 27 0.7s 346K
Level Assignment 0.8s 348K
Process Nets 0.8s 348K
Component Placement 0.8s 350K
Total Placement Component-Iterations = 217 0.8s 350K
Adjust Y Spacing 0.8s 351K
Channel Routing 0.8s 351K
Adjust X Spacing 0.8s 351K
Building Wires 0.8s 351K
Split page 28 0.8s 352K
Level Assignment 0.8s 354K
Process Nets 0.8s 354K
Component Placement 0.8s 354K
Total Placement Component-Iterations = 170 0.8s 354K
Adjust Y Spacing 0.8s 354K
Channel Routing 0.8s 355K
Adjust X Spacing 0.8s 355K
Building Wires 0.8s 355K
Split page 29 0.8s 356K
Level Assignment 0.8s 358K
Process Nets 0.8s 358K
Component Placement 0.8s 358K
Total Placement Component-Iterations = 129 0.8s 358K
Adjust Y Spacing 0.8s 358K
Channel Routing 0.8s 359K
Adjust X Spacing 0.8s 359K
Building Wires 0.8s 359K
Split page 30 0.8s 360K
Level Assignment 0.8s 362K
Process Nets 0.8s 362K
Component Placement 0.8s 364K
Total Placement Component-Iterations = 265 0.8s 364K
Adjust Y Spacing 0.8s 364K
Channel Routing 0.8s 364K
Adjust X Spacing 0.8s 364K
Building Wires 0.8s 364K
Split page 31 0.8s 366K
Level Assignment 0.8s 368K
Process Nets 0.8s 368K
Component Placement 0.8s 368K
Total Placement Component-Iterations = 144 0.8s 368K
Adjust Y Spacing 0.8s 368K
Channel Routing 0.8s 368K
Adjust X Spacing 0.9s 369K
Building Wires 0.9s 369K
Split page 32 0.9s 371K
Level Assignment 0.9s 372K
Process Nets 0.9s 372K
Component Placement 0.9s 373K
Total Placement Component-Iterations = 345 0.9s 373K
Adjust Y Spacing 0.9s 373K
Channel Routing 0.9s 373K
Adjust X Spacing 0.9s 373K
Building Wires 0.9s 374K
Split page 33 0.9s 375K
Level Assignment 0.9s 377K
Process Nets 0.9s 377K
Component Placement 0.9s 377K
Total Placement Component-Iterations = 119 0.9s 377K
Adjust Y Spacing 0.9s 377K
Channel Routing 0.9s 377K
Adjust X Spacing 0.9s 377K
Building Wires 0.9s 377K
Split page 34 0.9s 379K
Level Assignment 0.9s 380K
Process Nets 0.9s 380K
Component Placement 0.9s 383K
Total Placement Component-Iterations = 184 0.9s 383K
Adjust Y Spacing 0.9s 383K
Channel Routing 0.9s 383K
Adjust X Spacing 0.9s 383K
Building Wires 0.9s 383K
Split page 35 0.9s 385K
Level Assignment 0.9s 388K
Process Nets 0.9s 388K
Component Placement 0.9s 389K
Total Placement Component-Iterations = 392 0.9s 390K
Adjust Y Spacing 0.9s 390K
Channel Routing 0.9s 390K
Adjust X Spacing 0.9s 390K
Building Wires 0.9s 390K
Split page 36 0.9s 392K
Level Assignment 0.9s 395K
Process Nets 0.9s 395K
Component Placement 0.9s 396K
Total Placement Component-Iterations = 172 0.9s 396K
Adjust Y Spacing 0.9s 396K
Channel Routing 0.9s 396K
Adjust X Spacing 0.9s 396K
Building Wires 0.9s 396K
Split page 37 0.9s 398K
Level Assignment 0.9s 399K
Process Nets 0.9s 399K
Component Placement 0.9s 401K
Total Placement Component-Iterations = 421 0.9s 401K
Adjust Y Spacing 0.9s 401K
Channel Routing 0.9s 401K
Adjust X Spacing 0.9s 401K
Building Wires 0.9s 401K
Split page 38 0.9s 404K
Level Assignment 0.9s 406K
Process Nets 0.9s 406K
Component Placement 0.9s 409K
Total Placement Component-Iterations = 817 0.9s 409K
Adjust Y Spacing 0.9s 409K
Channel Routing 1.0s 409K
Adjust X Spacing 1.0s 410K
Building Wires 1.0s 410K
Split page 39 1.0s 413K
Level Assignment 1.0s 414K
Process Nets 1.0s 414K
Component Placement 1.0s 416K
Total Placement Component-Iterations = 384 1.0s 416K
Adjust Y Spacing 1.0s 416K
Channel Routing 1.0s 417K
Adjust X Spacing 1.0s 417K
Building Wires 1.0s 417K
Split page 40 1.0s 418K
Level Assignment 1.0s 420K
Process Nets 1.0s 420K
Component Placement 1.0s 426K
Total Placement Component-Iterations = 840 1.0s 426K
Adjust Y Spacing 1.0s 426K
Channel Routing 1.0s 427K
Adjust X Spacing 1.0s 427K
Building Wires 1.0s 427K
Split page 41 1.0s 429K
Level Assignment 1.0s 432K
Process Nets 1.0s 432K
Component Placement 1.0s 437K
Total Placement Component-Iterations = 1482 1.0s 437K
Adjust Y Spacing 1.0s 437K
Channel Routing 1.0s 438K
Adjust X Spacing 1.0s 438K
Building Wires 1.0s 438K
Split page 42 1.0s 441K
Level Assignment 1.0s 442K
Process Nets 1.0s 442K
Component Placement 1.0s 444K
Total Placement Component-Iterations = 516 1.1s 444K
Adjust Y Spacing 1.1s 444K
Channel Routing 1.1s 444K
Adjust X Spacing 1.1s 444K
Building Wires 1.1s 444K
Completed Schematic Generation, 22 Pages 1.1s 446K
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