Name

lca2vhd - converts an X4000 LCA file to a VHDL entity/architecture pair.

Syntax

lca2vhd [options] design

Description:

lca2vhd is a Perl5 script for converting a Xilinx LCA file into a VHDL entity/architecture pair which uses the X4000 model library from Mississippi State University. lca2vhd expects a design.lca file to be present in the current directory and will create design_x4000_.vhd (entity), and design_x4000_arch.vhd (architecture) files. The default arch name is 'behv' but this can be overridden on the command line. CLB,IOB, and other component timing values will be read from the design.spc file if it is present; else default timing values will be used. The design.spc can be generated via the '-s' flag to the Xilinx lca2vhd program. Any net delay information in the LCA file will also be present in the generated VHDL.

If the -xact option is not used, then the XACT environment variable must be set to the path of your Xilinx installation. lca2vhd reads information from Xilinx package files present in the '$XACT/data' directory.

Options

-arch name    Force the architecture name to be name. Default is behv

-net_simple    Use simple, internally-generated net names instead of original LCA net names converted to VHDL syntax requirements.

-name_len value    Max name length for converted names, default is 32 characters.

-xact path    path to Xilinx installation, use this instead of $XACT environment variable.

-map map_file

The map option will override port/net names used in the LCA file with those specified in the map_file. Each entry in the map file can be one of the following forms:


   pin  new_name old_name
   net  new_name old_name
   net  old_name
The keyword pin is used to override the name of an external port name. old_name refers to the name used within the LCA file; new_name is the name to be used within the generated VHDL entity/architecture pair. Common use of this form is to change a Viewlogic-generated port name which is part of a bus to a VHDL bus name such as: 


   pin  DATA(0) DATA0
The keyword net is used to override a net name used within the generated VHDL architecture. This is mainly used to aid debugging in that lca2vhd maps the LCA net names to internal net names to avoid problems with VHDL naming conventions; the net record allows the user to short-circuit this name remapping. When only old_name is present then the netname used in the LCA file will be used in the VHDL architecture with no change.

The keywords net, pin, are not case-sensitive; old_name is case-sensitive and must match the case used in the LCA file.

The entity file will NOT be generated if the -map option is used since it is expected that the user desires to supply a custom entity file. It will be necessary to let lca2vhd generate the entity at least once in order to get the values for the generics required by the architecture (these generics represent the component timings read from the .spc file and will only change if you change the package or speed grade). Thanks goes to Scott Bilik, Lockheed Sanders for suggesting the -map option.

Installation

You must edit the first line of the lca2vhd file to represent the path to your Perl5 binary. lca2vhd has been tested with Perl5 version 5.001.

Limitations

The MSU X4000 component models do not support boundary scan as of yet; lca2vhd will abort if it detects the use of a BSCAN component in the LCA file. The only functionality of the STARTUP component currently supported is global tristate and global reset. All X4000 functionality of the CLB, IOB, dedicated-carry logic, internal tri-state drivers, fast decoders, pullups and on-chip oscillator components is supported. The additional CLB functionality found in the X4000E family is not supported yet. Power-up functionality and timing is not supported yet. See the MSU Xilinx X4000 component model documentation for more discussion of the supported functionality/timing for the X4000 family.

Author
Bob Reese601/325-3670 (voice)
reese@erc.msstate.edu601/325-7692 (fax)
Microsystems Prototyping Laboratory, MSU/NSF Engr. Research Ctr.
Associate Prof/Electrical & Computer Engineering