History of the Benchmarks ========================= ------------------------------------------------------------------- 3.12.93 V0.8.1 Changed font for the texts from Palation to Times (for better compatibility) ------------------------------------------------------------------- 10.12.93 v0.8.2 Documentation smoothed ------------------------------------------------------------------- 13.12.93 v0.8.3 Documentation for Multiplier Benchmark added ------------------------------------------------------------------- 14.01.94 v0.8.4 Documentation for Divider Benchmark added ------------------------------------------------------------------- 28.01.94 v1.0.0 Documentation for FIFO Benchmark added Documentation for Associative Memory Benchmark added (parts still incomplete) Documentation for 1dim Systolic Array Benchmark added Documentation for 2dim Systolic Array Benchmark added Introductory text slightly changed ------------------------------------------------------------------- 14.03.94 v1.0.1 VHDL description "Assoc.vhdl" of the associative memory added Waveform "WAVEFORMAssoc.ps" of the associative memory added Basic VHDL Library "Library.vhdl" changed (some elements added) ------------------------------------------------------------------- 15.03.94 v1.0.2 Table 15-3 (FSM transition function of the GCD circuit) corrected (thanks to J.-L. Paillet) Equation (16-2) corrected (thanks to M. Kortke) Divider circuit partly reworked, due to various inconsitencies and errors (Chapter 17) (thanks to Geert Janssen) Specification of the Min-Max example marked as ambiguous Will be clarified in a future release, when an implementation will be added (thanks to Geert Janssen) ------------------------------------------------------------------- 17.03.94 v1.0.3 Associative Memory description completed ------------------------------------------------------------------- New version of base module library (Libarary.vhdl) ------------------------------------------------------------------- 14.11.94 v1.0.5 Introduction changed to reflect the new "official" status of the circuits ------------------------------------------------------------------- 17.11.95 v.1.1.0 VHDL descriptions of all existent circuit descriptions changed to make them SNOPSIS synthesizable. New basic cell libraries ELEMpack.vhd and GateLib.vhd ------------------------------------------------------------------- 11.4.95 v.1.2.0 Implementation descriptions added for - SinglePulser - n-Bit Adder - MinMax - StopWatch - Arbiter Some specification made more formal.