--
-- Rcsid[] = "$Id: alulogic.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This module is responsible for all the arithmetic and shift
-- operations.  It also contains the flag logic, and operand logic
-- for the ALU(including the TEMP ACCUMULATOR and AUX_ACCUMULATOR).

entity alulogic is
port(BO: out bit_vector(7 downto 0);
     BIN: in bit_vector(7 downto 0);
     WRACC,ACCOUTEN,WRAUXACC,WR2TEMP,TEMP_OUT: in bit;
	 MUXCC,MUXCCBAR: out bit;
     ID19,ID18,ID16,ID15,ID14,ID13,ID12,ID11,ID10,ID9,ID8,ID7,ID6,ID5,ID4,ID1: in bit;
     I5,I4,I3,M3,M2,M1,T4,T3,T2: in bit;
     VCC,GND,CLKBAR,ALUOUTEN,REGRESET,ENBUSTOAUX: in bit);
end;

architecture structure of alulogic is

component ALU_8BIT
port(F: out bit_vector(7 downto 0);
     A_eq_B, X, Y, Z, AC, P, CY: out bit;
     S: in bit_vector(3 downto 0);
     A: in bit_vector(7 downto 0);
     B: in bit_vector(7 downto 0);
     Cn, M: in bit);
end component;

component oprlogic
port(BO7,  BO6,  BO5,  BO4,  BO3,  BO2,  BO1,  BO0: out bit;
	 ALUA,ALUB: out bit_vector(7 downto 0);
     BIN7,BIN6,BIN5,BIN4,BIN3,BIN2,BIN1,BIN0,
	 WRACC,ACCOUTEN,WRAUXACC,WR2TEMP,TEMP_OUT,VCC,GND,CLK,
     T4,T2,AC_buf,CY,CLEAR, ID4,ID7,ID12,ID16,ENBUSTOAUX: in bit);
end component;

component alu_ctrl
port(M,S0,S1,S2,S3,ENABLEDCY: out bit;
	 ID1,ID4,ID6,ID7,ID8: in  bit;
	 ID9,ID10,ID11,ID12,ID13,ID14: in bit;
	 ID15,ID16,ID18,ID19,I3,M3,CY,ID5: in bit);
end component;

component flagunit
port(BUSOUT0,BUSOUT4,BUSOUT6,BUSOUT2,BUSOUT7,MUXCC,MUXCCBAR,ALUCYOUT,AC_SET: out bit;
     M3,M2,M1,T4,T3,T2,
     IBUS0,IBUS2,IBUS4,IBUS6,IBUS7,ALUCRYIN,ACFLAG,ZFLAG,
     PFLAG,SFLAG,I3,CLKBAR,GND,VCC,
     ID1,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,ID13,ID14,ID15,ID16,ID18,ID19: in bit);
end component;

component shflogic
port(CARRYOUT: out bit;
      BO: out bit_vector(7 downto 0);
--      ALU7,ALU6,ALU5,ALU4,ALU3,ALU2,ALU1,ALU0,
     ALU: in bit_vector(7 downto 0);
	  CNPLUS4BAR,I3,I4,I5,ID7,ID16,ID15,ALUOUTEN,CARRYIN: in bit);
end component;

signal F: bit_vector(7 downto 0);
signal S3, S2, S1, S0: bit;
signal A,B: bit_vector(7 downto 0);
signal M, Cn, CY, CNPLUS4BAR, ACSET: bit;
signal AC_buf : bit;
signal P, Z, CARRYOUT: bit;

begin
-- alu_8bit contains the 8 bit ALU
A_8B : alu_8bit port map(F(7 downto 0),OPEN,OPEN,OPEN,Z,AC_buf,
              P,CNPLUS4BAR,S3,S2,S1,S0,A(7 downto 0), B(7 downto 0),Cn,M);
OP_L : oprlogic port map(BO(7 downto 0),A(7 downto 0),B(7 downto 0),
              BIN(7 downto 0),
              WRACC,ACCOUTEN,WRAUXACC, WR2TEMP,TEMP_OUT,
              VCC,GND,CLKBAR,T4,T2,ACSET,CY,
              REGRESET,ID4,ID7,ID12,ID16,ENBUSTOAUX);
AL_C : alu_ctrl port map(M,S0,S1,S2,S3,Cn,ID1,ID4,ID6,ID7,ID8,
              ID9,ID10,ID11,ID12,ID13,ID14,ID15,ID16,ID18,
              ID19,I3,M3,CY,ID5);
FG_U : flagunit port map(BO(0),BO(4),BO(6),BO(2),BO(7),MUXCC,MUXCCBAR,CY,ACSET,
              M3,M2,M1,T4,T3,T2,
              BIN(0),BIN(2),BIN(4),BIN(6),BIN(7),CARRYOUT,AC_buf,Z,
              P,F(7),I3,CLKBAR,GND,VCC,
              ID1,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,ID13,ID14,ID15,ID16,ID18,ID19);
SH_L : shflogic port map(CARRYOUT,BO(7 downto 0),
              F(7 downto 0),CNPLUS4BAR,I3,I4,I5,
              ID7,ID16,ID15,ALUOUTEN,CY);
end structure;

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