Schematic Diagram and Source for Reference Design(DIGCAM) Version 1.2

Description

Version 1.2 of the DIGCAM is designed with a two level bus structure. The bus structure is designed as follows:

Main System Bus

• High speed bus
• 32-bit data width

Peripheral Bus

• Slow speed bus
• ISA protocol
• 32-bit and 8-bit data width available

In an effort to increase the speed at which the DIGCAM operates, we added a peripheral write buffer to the BRIDGE such that the MIPS would not be blocked while a peripheral write completes. There are three configurations of the bridge with 0, 1, and 2 words write buffers respectively.

Readme briefly describes steps that are needed to follow.

readme.txt

Source Code and Script Files for 32-bit Peripheral Bus

Core source codes and synthesis scripts:

• BIOS.vhd
• BIOS_syn.scr
• BRIDGE0.vhd
• BRIDGE1.vhd
• BRIDGE2.vhd
• BRIDGE_syn0.scr
• BRIDGE_syn1.scr
• BRIDGE_syn2.scr
• CCD.vhd
• CCD_syn.scr
• CODEC.vhd
• CODEC_syn.scr
• MEMORY.vhd
• MEMORY_syn.scr
• MIPS.vhd
• MIPS_syn.scr
• PC16550.vhd
• PC16550_syn.scr
• PPP.vhd (8255A)
• PPP_syn.scr
• DIG_CAM.vhd
• DIG_CAM_syn0.scr
• DIG_CAM_syn1.scr
• DIG_CAM_syn2.scr
• DIG_CAM_TB.vhd (Testbench)

Scripts for analyzing and synthesizing design:

• compile.scr (Used by synthesis scripts above)
• vhdlan.scr Analyze behavioral design
• vhdlan_syn.scr Analyze Gate-level design
• syn.scr Synthesize design

Scripts used for power analysis:

• sim0.scr Simulates design capturing statistics
• sim1.scr Simulates design capturing statistics
• sim2.scr Simulates design capturing statistics
• run0.scr (Used in sim0.scr)
• run1.scr (Used in sim1.scr)
• run2.scr (Used in sim2.scr)
• power.scr0 Average Bus:Internal Ratio
• power.scr1 Average Bus:Internal Ratio
• power.scr2 Average Bus:Internal Ratio
• power_high0.scr High Bus:Internal Ratio
• power_high1.scr High Bus:Internal Ratio
• power_high2.scr High Bus:Internal Ratio

Source Code and Script Files for 8-bit Peripheral Bus

Core source codes and synthesis scripts:

• BIOS.vhd
• BIOS_syn.scr
• BRIDGE0.vhd
• BRIDGE1.vhd
• BRIDGE2.vhd
• BRIDGE_syn0.scr
• BRIDGE_syn1.scr
• BRIDGE_syn2.scr
• CCD.vhd
• CCD_syn.scr
• CODEC.vhd
• CODEC_syn.scr
• MEMORY.vhd
• MEMORY_syn.scr
• MIPS.vhd
• MIPS_syn.scr
• PC16550.vhd
• PC16550_syn.scr
• PPP.vhd (8255A)
• PPP_syn.scr
• DIG_CAM.vhd
• DIG_CAM_syn0.scr
• DIG_CAM_syn1.scr
• DIG_CAM_syn2.scr
• DIG_CAM_TB.vhd (Testbench)

Scripts for analyzing and synthesizing design:

• compile.scr (Used by synthesis scripts above)
• vhdlan.scr Analyze behavioral design
• vhdlan_syn.scr Analyze Gate-level design
• syn.scr Synthesize design

Scripts used for power analysis:

• sim0.scr Simulates design capturing statistics
• sim1.scr Simulates design capturing statistics
• sim2.scr Simulates design capturing statistics
• run0.scr (Used in sim0.scr)
• run1.scr (Used in sim1.scr)
• run2.scr (Used in sim2.scr)
• power.scr0 Average Bus:Internal Ratio
• power.scr1 Average Bus:Internal Ratio
• power.scr2 Average Bus:Internal Ratio
• power_high0.scr High Bus:Internal Ratio
• power_high1.scr High Bus:Internal Ratio
• power_high2.scr High Bus:Internal Ratio