analyze -format vhdl -lib WORK {"PC16550.vhd"}
elaborate CFG_PC16550 -lib DEFAULT -update

include compile.scr

vhdlout_top_configuration_name = "CFG_PC16550_SYN"
vhdlout_top_configuration_entity_name = "PC16550"

write -format db -hierarchy -output "PC16550_GATE.db"
write -format vhdl -hierarchy -output "PC16550_GATE.vhd"

report_area

exit