read DIG_CAM_GATE0.db

set_operating_conditions -library "lsi_10k" "WCCOM"
set_wire_load  "10x10" -library "lsi_10k"
set_driving_cell -cell AN2P -library lsi_10k all_inputs()

create_clock find(port, "clk") -period 5

set_load 1000 find(net, "*", -hierarchy)
set_load 206000 find(net, "addr*");
set_load 206000 find(net, "rd");
set_load 206000 find(net, "wr");
set_load 206000 find(net, "data*")
set_load 206000 find(net, "rdy");
set_load 206000 find(net, "paddr*");
set_load 51500 find(net, "pdata*");
set_load 206000 find(net, "ior");
set_load 206000 find(net, "iow");
set_load 206000 find(net, "ale");
set_load 206000 find(net, "iochrdy");

include dig_cam_sa0.scr

check_design

report_power -cumulative -net -analysis_effort high
report_power -analysis_effort high

exit