--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 12/31/98
-- Version 1.2
-- Notes: Test Bench for DIG_CAM.
--

--**************************************************************************--

library IEEE;
library lsi_10k;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use lsi_10k.all;

--**************************************************************************--

entity DIG_CAM_TB is
end DIG_CAM_TB;

--**************************************************************************--

architecture BHV_DIG_CAM_TB of DIG_CAM_TB is

	--
	-- component declarations
	--
	component DIG_CAM
		port( scan_clk : in STD_LOGIC;
                      scan_data : in UNSIGNED(7 downto 0);
		      clk : in STD_LOGIC;
		      rst : in STD_LOGIC );
	end component;

	--
	-- component library binding
	--
	--for all : DIG_CAM use entity WORK.DIG_CAM(BHV_DIG_CAM);

	--
	-- signal declarations
	--
	signal scan_clk : STD_LOGIC := '0';
	signal scan_data : UNSIGNED(7 downto 0) := "00000000";
	signal clk, rst : STD_LOGIC := '0';
begin
	process
	begin
		rst <= '1';
		wait for 10 ns;
		rst <= '0';
		wait;
	end process;

	--
	-- clock generator
	--
	scan_clk <= not scan_clk after 2 ns;
	scan_data <= scan_clk & 
                     (not clk) & 
                     (not scan_clk) &
                     (scan_clk or clk) &
                     (scan_clk xor clk) &
                     (scan_clk and not clk) &
                     (not scan_clk xor clk) &
                     (clk);

	clk <= not clk after 5 ns;
	
	--
	-- component instantiation
	--
	DIG_CAM_1 : DIG_CAM port map(scan_clk, scan_data, clk, rst);
end BHV_DIG_CAM_TB;

--**************************************************************************--

configuration CFG_DIG_CAM_TB of DIG_CAM_TB is
	for BHV_DIG_CAM_TB
--		for DIG_CAM_1 : DIG_CAM use configuration WORK.CFG_DIG_CAM;
--		end for;
	end for;
end CFG_DIG_CAM_TB;

-- end of file --