--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 12/31/98
-- Version 1.2
-- Notes: Test Bench for DIG_CAM.
--

--**************************************************************************--

library IEEE;
library lsi_10k;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use lsi_10k.all;

--**************************************************************************--

entity DIG_CAM_TB is
end DIG_CAM_TB;

--**************************************************************************--

architecture BHV_DIG_CAM_TB of DIG_CAM_TB is

	--
	-- constant declarations
	--
	constant C0_32 : UNSIGNED(31 downto 0) :=
		"00000000000000000000000000000000";

	constant C0_24 : UNSIGNED(23 downto 0) :=
		"000000000000000000000000";

	constant C0_8 : UNSIGNED(7 downto 0) :=
		"00000000";

	constant COMPRESSION : INTEGER range 1 to 4 := 4;
	constant IMAGE_HEIGHT : INTEGER := 16;	
	constant IMAGE_WIDTH : INTEGER := 16;	
	constant IMAGE_SIZE : INTEGER := IMAGE_HEIGHT * IMAGE_WIDTH;

	-- 
	-- type declaration
	--
	subtype MEM_CELL is UNSIGNED(31 downto 0);
	type MEM_TYPE is array((IMAGE_WIDTH*IMAGE_WIDTH-1) downto 0) 
		of MEM_CELL;
	type STATE_TYPE is (IDLE,CHECK,DONE, ASSERT_RESULT);

	--
	-- component declarations
	--
	component DIG_CAM 
		generic(COMPRESSION : INTEGER range 1 to 4 := 4);
		port(	scan_clk : in STD_LOGIC;
			scan_data : in UNSIGNED(7 downto 0);
			clk : in STD_LOGIC;
			rst : in STD_LOGIC;
			start_capture: out STD_LOGIC;
			rd_out : out STD_LOGIC;
			wr_out : out STD_LOGIC;
			ior_out : out STD_LOGIC;
			iow_out : out STD_LOGIC;
			data_out: out UNSIGNED(31 downto 0);
			addr_out: out UNSIGNED(22 downto 0) );
	end component;

	--
	-- signal declarations
	--
	signal scan_clk : STD_LOGIC := '0';
	signal scan_data : UNSIGNED(7 downto 0) := "00000000";
	signal clk, rst : STD_LOGIC := '0';
	signal data: UNSIGNED(31 downto 0);
	signal addr: UNSIGNED(22 downto 0); 
	signal start_capture: STD_LOGIC := '0';
	signal image : MEM_TYPE;
	signal cmp_image : MEM_TYPE;
	signal check_start : STD_LOGIC := '0';
	signal check_done : STD_LOGIC := '0';
	signal check_ok : STD_LOGIC := '0';
	signal check_fail : STD_LOGIC := '0';
	signal rd, wr : STD_LOGIC;
	signal ior, iow : STD_LOGIC;
	signal start_monitor : STD_LOGIC := '0';
	signal MAX_MEM : INTEGER := 350;
	signal CODEC_ADDR : INTEGER := 1025;
	signal state : STATE_TYPE := IDLE;
	signal location: INTEGER := 0;
	signal bias: UNSIGNED(7 downto 0) := C0_8;

begin
	process
	begin
		rst <= '1';
		wait for 10 ns;
		rst <= '0';
		wait;
	end process;

	--
	-- image capture/compression process
	--
	process(scan_clk)
		variable location : INTEGER := 0;
		variable temp, temp2, temp3 : INTEGER := 0;
	begin
		
		if(scan_clk'event and scan_clk = '1') then

			if (location < IMAGE_SIZE) then
				if(start_capture = '1') then

					if(temp3 = 16) then

						temp3 := 0;
						bias <= scan_data;
					else
						image(location) <= C0_24 & 
							(scan_data - bias);
						cmp_image(location) <= C0_32;
						location := location +1;
						temp3 := temp3 + 1;

					end if;
				end if;

			elsif(location = IMAGE_SIZE) then

				for position in 0 to (IMAGE_SIZE / COMPRESSION)-1 loop

					for temp in 0 to COMPRESSION-1 loop
						temp2 := temp * 8;
						cmp_image(position)(temp2+7 downto temp2) <= 
							image(position*COMPRESSION +temp)(7 downto 0);
					end loop;
				end loop;

				location := location + 1;
			end if;
		end if;
	end process;

	--
	-- compressed image check process
	--
	process(clk)
	begin

		if(clk'event and clk = '1') then

			case(state) is

			when IDLE =>

				if(wr = '1' or rd = '1') then
					if(addr = conv_integer(CODEC_ADDR)) then
						state <= CHECK;
					end if;
				end if;

			when CHECK =>

				if (wr = '1') then

					if (location < (IMAGE_SIZE / COMPRESSION) ) then
						if(addr < conv_integer(MAX_MEM)) then
							check_start <= '1';	
							if(data /= cmp_image(location)) then
								check_fail <= '1';
								state <= DONE;
							end if;
							location <= location + 1;
						end if;
					else
						state <= DONE;
					end if;
				end if;

			when DONE =>

				check_ok <= not check_fail;
				check_done <= '1';
				state <= ASSERT_RESULT;

			when ASSERT_RESULT =>
				
				assert(check_ok = '1') 
					report "Error capturing image!" severity failure;
				assert(check_fail = '1') 
					report "Successfully captured image" severity failure;

			end case;
		end if;
	end process;


	--
	-- clock generator
	--
	scan_clk <= not scan_clk after 5 ns;

	scan_data <= scan_data + 1 after 10 ns;

	clk <= not clk after 10 ns;

	--
	-- component instantiation
	--
	DIG_CAM_1 : DIG_CAM generic map ( COMPRESSION )
				port map( scan_clk, scan_data, clk, rst,
					  start_capture, rd, wr, ior, iow,
					  data, addr);
end BHV_DIG_CAM_TB;

--**************************************************************************--

configuration CFG_DIG_CAM_TB of DIG_CAM_TB is
	for BHV_DIG_CAM_TB
	end for;
end CFG_DIG_CAM_TB;

-- end of file --