--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity PLAY is 
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     memadl : in STD_LOGIC_VECTOR (7 downto 0);
	     memadh : in STD_LOGIC_VECTOR (7 downto 0);
	     upp0 : in STD_LOGIC_VECTOR (7 downto 0);
	     upwr : in STD_LOGIC;
	     spk : out STD_LOGIC);
end PLAY;

--**************************************************************************--

architecture PLAY_ARCH of PLAY is

	constant C0_16 : UNSIGNED (15 downto 0) := "0000000000000000";
	constant C1_16 : UNSIGNED (15 downto 0) := "0000000000000001";

	constant F1_A  : UNSIGNED (15 downto 0) := "";  -- 440.00  HZ
	constant F1_AS : UNSIGNED (15 downto 0) := "";  -- 466.16  HZ
	constant F1_B  : UNSIGNED (15 downto 0) := "";  -- 493.908 HZ
	constant F1_C  : UNSIGNED (15 downto 0) := "";  -- 523.24  HZ
	constant F1_CS : UNSIGNED (15 downto 0) := "";  -- 554.37  HZ
	constant F1_D  : UNSIGNED (15 downto 0) := "";  -- 587.31  HZ
	constant F1_DS : UNSIGNED (15 downto 0) := "";  -- 622.27  HZ
	constant F1_E  : UNSIGNED (15 downto 0) := "";  -- 659.26  HZ
	constant F1_F  : UNSIGNED (15 downto 0) := "";  -- 698.48  HZ
	constant F1_FS : UNSIGNED (15 downto 0) := "";  -- 740.00  HZ
	constant F1_G  : UNSIGNED (15 downto 0) := "";  -- 784.00  HZ
	constant F1_GS : UNSIGNED (15 downto 0) := "";  -- 830.56  HZ

	constant F2_A  : UNSIGNED (15 downto 0) := "";  -- These notes are
	constant F2_AS : UNSIGNED (15 downto 0) := "";  -- the same are equaled
	constant F2_B  : UNSIGNED (15 downto 0) := "";  -- to the F1 notes
	constant F2_C  : UNSIGNED (15 downto 0) := "";  -- divided by 2
	constant F2_CS : UNSIGNED (15 downto 0) := "";
	constant F2_D  : UNSIGNED (15 downto 0) := "";
	constant F2_DS : UNSIGNED (15 downto 0) := "";
	constant F2_E  : UNSIGNED (15 downto 0) := "";
	constant F2_F  : UNSIGNED (15 downto 0) := "";
	constant F2_FS : UNSIGNED (15 downto 0) := "";
	constant F2_G  : UNSIGNED (15 downto 0) := "";
	constant F2_GS : UNSIGNED (15 downto 0) := "";

	constant F3_A  : UNSIGNED (15 downto 0) := "";  -- These notes are
	constant F3_AS : UNSIGNED (15 downto 0) := "";  -- the same are equaled
	constant F3_B  : UNSIGNED (15 downto 0) := "";  -- to the F2 notes
	constant F3_C  : UNSIGNED (15 downto 0) := "";  -- divided by 2
	constant F3_CS : UNSIGNED (15 downto 0) := "";
	constant F3_D  : UNSIGNED (15 downto 0) := "";
	constant F3_DS : UNSIGNED (15 downto 0) := "";
	constant F3_E  : UNSIGNED (15 downto 0) := "";
	constant F3_F  : UNSIGNED (15 downto 0) := "";
	constant F3_FS : UNSIGNED (15 downto 0) := "";
	constant F3_G  : UNSIGNED (15 downto 0) := "";
	constant F3_GS : UNSIGNED (15 downto 0) := "";
	
	constant REG_ADDRH : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; 
	constant REG_ADDRL : STD_LOGIC_VECTOR (7 downto 0) := "00000000";

	signal clk_div, clk_cnt : UNSIGNED (15 downto 0);
	signal toggle : STD_LOGIC;
begin
	--
	-- sound generator
	--
	process(rst, clk, toggle)
	begin
		if( rst = '0' ) then
			
			clk_cnt <= C0_16;
			toggle <= '0';
			spk <= '1';
		elsif( clk'event and clk = '1' ) then
		
                        -- finsih the clock divider code
                        -- toggle value is the signal being output
                        -- so when clock divider has reached max
                        -- simply invert the toggle value 
                  
		end if;
		
		spk <= toggle;
	end process;
	
	--
	-- cpu write and note generator
	--
	process(rst, clk)
	begin
		if( rst = '0' ) then

			clk_div <= C0_16;
		elsif( clk'event and clk = '1' ) then
		
			if( upwr = '0' ) then
			
				if( memadh = REG_ADDRH and memadl = REG_ADDRL ) then
 			
					case upp0 is
						-- octave 1
						when "00000000" => clk_div <= F1_A; 
                                                -- finish octave 1 assignments

                                                                   
						-- octave 2
                                                -- finish octave 2 assignments
						
						-- octave 3
                                                -- finish octave 3 assignments  
						
						when others     => clk_div <= C0_16;
					end case;
				end if;
			end if;
		end if;
	end process;
end PLAY_ARCH;