--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity XS40 is 
	port(rst : in STD_LOGIC;
             clk : in STD_LOGIC;
             led : out STD_LOGIC_VECTOR (6 downto 0);
             uprst : out STD_LOGIC;
             upclk : out STD_LOGIC;
	     uppsen : in STD_LOGIC;
	     upale : in STD_LOGIC;
	     uprd : in STD_LOGIC;
	     upwr : in STD_LOGIC;
	     upp0 : inout STD_LOGIC_VECTOR (7 downto 0);
	     upp1 : in STD_LOGIC_VECTOR (3 downto 0);
	     memadl : inout STD_LOGIC_VECTOR (7 downto 0);
	     memadh : in STD_LOGIC_VECTOR (7 downto 0);
	     memoe : out STD_LOGIC;
	     memcs : out STD_LOGIC;
	     spk : out STD_LOGIC);
end XS40;

--**************************************************************************--

architecture XS40_ARCH of XS40 is

	component WRLED
		port(val : in UNSIGNED (3 downto 0);
		     led : out STD_LOGIC_VECTOR (6 downto 0));
	end component;

	component CTRUP
		port(rst : in STD_LOGIC;
		     clk : in STD_LOGIC;
		     uprst : out STD_LOGIC;
		     upclk : out STD_LOGIC;
		     uppsen : in STD_LOGIC;
		     upale : in STD_LOGIC;
		     upp0 : in STD_LOGIC_VECTOR (7 downto 0);
		     uprd : in STD_LOGIC;
		     memadl : out STD_LOGIC_VECTOR (7 downto 0);
		     memoe : out STD_LOGIC;
		     memcs : out STD_LOGIC);
	end component;
	
	component PLAY 
		port(rst : in STD_LOGIC;
		     clk : in STD_LOGIC;
		     memadl : in STD_LOGIC_VECTOR (7 downto 0);
		     memadh : in STD_LOGIC_VECTOR (7 downto 0);
		     upp0 : in STD_LOGIC_VECTOR (7 downto 0);
		     upwr : in STD_LOGIC;
		     spk : out STD_LOGIC);
	end component;
		
	constant C0_4 : UNSIGNED (3 downto 0) := "0000";
	
	signal val : UNSIGNED (3 downto 0);
begin
	U1 : WRLED port map(VAL, LED);
	U2 : CTRUP port map(rst, clk, uprst, upclk, uppsen, upale, upp0, uprd, memadl, memoe, memcs);
	U3 : PLAY port map(rst, clk, memadl, memadh, upp0, upwr, spk);
		
	process(rst, clk)
	begin
		if( rst = '0' ) then

			val <= C0_4;
		elsif( clk'event and clk = '1' ) then

			val <= UNSIGNED(upp1);
		end if;
	end process;
end XS40_ARCH;