--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity CTRUP is 
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     uprst : out STD_LOGIC;
	     upclk : out STD_LOGIC;
	     uppsen : in STD_LOGIC;
	     upale : in STD_LOGIC;
	     upp0 : in STD_LOGIC_VECTOR (7 downto 0);
	     uprd : in STD_LOGIC;
	     memadl : out STD_LOGIC_VECTOR (7 downto 0);
	     memoe : out STD_LOGIC;
	     memcs : out STD_LOGIC);
end CTRUP;

--**************************************************************************--

architecture CTRUP_ARCH of CTRUP is

	constant C1_8 : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
begin
	-- reset and clock
	uprst <= not rst;
	upclk <= clk;		-- this causes a harmless warning
	
	-- enable memory
	memcs <= '0';
	memoe <= uppsen and uprd;
	
	-- lower address latch
	process(rst, upale)
	begin
		if( rst = '0' ) then
		
			memadl <= C1_8;
		elsif( upale'event and upale = '0' ) then

			memadl <= upp0;
		end if;
	end process;
end CTRUP_ARCH;